The fault analysis of analog circuits at subnetwork-level is confronted with two essentialcore problems: (ⅰ) Is it necessary that all the torn nodes are accessible? (ⅱ) Are there any topological conditions of subnet...The fault analysis of analog circuits at subnetwork-level is confronted with two essentialcore problems: (ⅰ) Is it necessary that all the torn nodes are accessible? (ⅱ) Are there any topological conditions of subnetwork which guarantee the fault at subnetwork-level to bediagnosed correctly? This paper answers the two problems in two theorems. The conditions are necessary and almost sufficient, and if all the torn nodes are accessible, the required topological conditions can be almost satisfied automatically. This is a special situation of our research on the distribution of the accessible nodes.展开更多
基金Project supported by the National Natural Science Foundation of China
文摘The fault analysis of analog circuits at subnetwork-level is confronted with two essentialcore problems: (ⅰ) Is it necessary that all the torn nodes are accessible? (ⅱ) Are there any topological conditions of subnetwork which guarantee the fault at subnetwork-level to bediagnosed correctly? This paper answers the two problems in two theorems. The conditions are necessary and almost sufficient, and if all the torn nodes are accessible, the required topological conditions can be almost satisfied automatically. This is a special situation of our research on the distribution of the accessible nodes.
