This paper presents the design and implement ofa CMOS smart temperature sensor, which consists of a low power analog front-end and a 12-bit low-power successive approximation register （SAR） analog-to-digital convert...This paper presents the design and implement ofa CMOS smart temperature sensor, which consists of a low power analog front-end and a 12-bit low-power successive approximation register （SAR） analog-to-digital converter （ADC）. The analog front-end generates a proportional-to-absolute-temperature （PTAT） voltage with MOS- FET circuits operating in the sub-threshold region. A reference voltage is also generated and optimized in order to minimize the temperature error and the 12-bit SAR ADC is used to digitize the PTAT voltage. Using 0.18 μm CMOS technology, measurement results show that the temperature error is -0.69/＋0.85 ℃ after one-point calibra- tion over a temperature range of-40 to 100 ℃. Under a conversion speed of 1K samples/s, the power consumption is only 2.02 μW while the chip area is 230 × 225 μm2, and it is suitable for RFID application.展开更多
This paper proposes a high-resolution successive-approximation register（SAR） analog-to-digital converter（ADC） with sub-2 radix split-capacitor array architecture.The built-in redundancy of sub-2 radix architecture...This paper proposes a high-resolution successive-approximation register（SAR） analog-to-digital converter（ADC） with sub-2 radix split-capacitor array architecture.The built-in redundancy of sub-2 radix architecture provides additional information in the digital calibration based on offset double injection.The calibration method is simple in structure and fast in convergence.The correction of errors in each bit is independent of those in the previous bit.A split-capacitor array is used to reduce the total capacitance especially in a high-resolution SAR ADC.An offset signal is injected by the switching scheme of capacitor array to minimize the hardware overhead.The prototype of 0.18 μm CMOS process obtains 14.46 bit ENOB and 95.65 dB SFDR after calibration.With calibration,the INL and DNL are-0.813/0.938 and-0.625/0.688,respectively.展开更多
A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier（THA） in 0.13μm CMOS for an impulse radio ultra-wideband（IR-UWB） receiver is presented.The challenge is in implementing a sub-samplin...A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier（THA） in 0.13μm CMOS for an impulse radio ultra-wideband（IR-UWB） receiver is presented.The challenge is in implementing a sub-sampling ADC with ultra-high input signal that further exceeds the Nyquist frequency.This paper presents,to our knowledge for the second time,a sub-sampling ADC with input signals above 4 GHz operating at a sampling rate of 1.056 GHz.In this design,a novel THA is proposed to solve the degradation in amplitude and improve the linearity of signal with frequency increasing to giga Hz.A resistive averaging technique is carefully analyzed to relieve noise aliasing.A low-offset latch using a zero-static power dynamic offset cancellation technique is further optimized to realize the requirements of speed,power consumption and noise aliasing.The measurement results reveal that the spurious free dynamic range of the ADC is 30.1 dB even if the input signal is 4.2 GHz sampled at 1.056 GS/s.The core power of the ADC is 30 mW,excluding all of the buffers,and the active area is 0.6 mm^2.The ADC achieves a figure of merit of 3.75 pJ/conversion-step.展开更多
基金supported by the Wuxi Special Funds for Development of Internet of Things of China(No.0414B011601130083PB)
文摘This paper presents the design and implement ofa CMOS smart temperature sensor, which consists of a low power analog front-end and a 12-bit low-power successive approximation register （SAR） analog-to-digital converter （ADC）. The analog front-end generates a proportional-to-absolute-temperature （PTAT） voltage with MOS- FET circuits operating in the sub-threshold region. A reference voltage is also generated and optimized in order to minimize the temperature error and the 12-bit SAR ADC is used to digitize the PTAT voltage. Using 0.18 μm CMOS technology, measurement results show that the temperature error is -0.69/＋0.85 ℃ after one-point calibra- tion over a temperature range of-40 to 100 ℃. Under a conversion speed of 1K samples/s, the power consumption is only 2.02 μW while the chip area is 230 × 225 μm2, and it is suitable for RFID application.
文摘This paper proposes a high-resolution successive-approximation register（SAR） analog-to-digital converter（ADC） with sub-2 radix split-capacitor array architecture.The built-in redundancy of sub-2 radix architecture provides additional information in the digital calibration based on offset double injection.The calibration method is simple in structure and fast in convergence.The correction of errors in each bit is independent of those in the previous bit.A split-capacitor array is used to reduce the total capacitance especially in a high-resolution SAR ADC.An offset signal is injected by the switching scheme of capacitor array to minimize the hardware overhead.The prototype of 0.18 μm CMOS process obtains 14.46 bit ENOB and 95.65 dB SFDR after calibration.With calibration,the INL and DNL are-0.813/0.938 and-0.625/0.688,respectively.
基金Project supported by the National High Technology Research and Development Program of China(No.2009AA01Z261)the State Key Laboratory of Wireless Telecommunication,Southeast University
文摘A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier（THA） in 0.13μm CMOS for an impulse radio ultra-wideband（IR-UWB） receiver is presented.The challenge is in implementing a sub-sampling ADC with ultra-high input signal that further exceeds the Nyquist frequency.This paper presents,to our knowledge for the second time,a sub-sampling ADC with input signals above 4 GHz operating at a sampling rate of 1.056 GHz.In this design,a novel THA is proposed to solve the degradation in amplitude and improve the linearity of signal with frequency increasing to giga Hz.A resistive averaging technique is carefully analyzed to relieve noise aliasing.A low-offset latch using a zero-static power dynamic offset cancellation technique is further optimized to realize the requirements of speed,power consumption and noise aliasing.The measurement results reveal that the spurious free dynamic range of the ADC is 30.1 dB even if the input signal is 4.2 GHz sampled at 1.056 GS/s.The core power of the ADC is 30 mW,excluding all of the buffers,and the active area is 0.6 mm^2.The ADC achieves a figure of merit of 3.75 pJ/conversion-step.
