A fault tolerant control （FTC） design technique against actuator stuck faults is investigated using integral-type sliding mode control （ISMC） with application to spacecraft attitude maneuvering control system. The...A fault tolerant control （FTC） design technique against actuator stuck faults is investigated using integral-type sliding mode control （ISMC） with application to spacecraft attitude maneuvering control system. The principle of the proposed FTC scheme is to design an integral-type sliding mode attitude controller using on-line parameter adaptive updating law to compensate for the effects of stuck actuators. This adaptive law also provides both the estimates of the system parameters and external disturbances such that a prior knowledge of the spacecraft inertia or boundedness of disturbances is not required. Moreover, by including the integral feedback term, the designed controller can not only tolerate actuator stuck faults, but also compensate the disturbances with constant components. For the synthesis of controller, the fault time, patterns and values are unknown in advance, as motivated from a practical spacecraft control application. Complete stability and performance analysis are presented and illustrative simulation results of application to a spacecraft show that high precise attitude control with zero steady-error is successfully achieved using various scenarios of stuck failures in actuators.展开更多
A nonlinear robust trajectory tracking strategy for a gliding hypersonic vehicle with an aileron stuck at an unknown position is presented in this paper. First, the components of translational motion dynamics perpendi...A nonlinear robust trajectory tracking strategy for a gliding hypersonic vehicle with an aileron stuck at an unknown position is presented in this paper. First, the components of translational motion dynamics perpendicular to the velocity are derived, and then a guidance law based on a time-varying sliding mode method is used to realize trajectory tracking. Furthermore, the rotational equations of motion are separated into an actuated subsystem and an unactuated subsystem. And an adaptive time-varying sliding mode attitude controller is proposed based on the actuated subsystem to track the command attitude and the tracking performance and robustness are therefore enhanced. The proposed guidance law and attitude controller make the hypersonic vehicle fly along the reference trajectory even when the aileron is stuck at an unknown angle. Finally, a hypersonic benchmark platform is used to demonstrate the effectiveness of the proposed strategy.展开更多
A stuck drill string results in a major non-productive cost in extended reach drilling engineering. The first step is to determine the depth at which the sticking has occurred. Methods of measurement have been proved ...A stuck drill string results in a major non-productive cost in extended reach drilling engineering. The first step is to determine the depth at which the sticking has occurred. Methods of measurement have been proved useful for determining the stuck points, but these operations take considerable time. As a result of the limitation with the current operational practices, calculation methods are still preferred to estimate the stuck point depth. Current analytical methods do not consider friction and are only valid for vertical rather than extended reach wells. The numerical method is established to take full account of down hole friction, tool joint, upset end of drill pipe, combination drill strings and tubular materials so that it is valid to determine the stuck point in extended reach wells. The pull test, torsion test and combined test of rotation and pulling can be used to determine the stuck point. The results show that down hole friction, tool joint, upset end of drill pipe, tubular sizes and materials have significant effects on the pull length and/or the twist angle of the stuck drill string.展开更多
According to New York Times on November 19, as retailers battle to draw customers into their stores on Black Friday, online merchants are plotting a cunning ambush, offering an arsenal of mobile-only deals intended to...According to New York Times on November 19, as retailers battle to draw customers into their stores on Black Friday, online merchants are plotting a cunning ambush, offering an arsenal of mobile-only deals intended to pick off shoppers as they wait in line. The Gilt Groupe, for example, which展开更多
Transverse process syndrome of the third lumbar vertebra is a common cause of lumbago and sciatica It is manifested by localized soreness, distention and pain on unilateral or bilateral aspect of the third lumbar tran...Transverse process syndrome of the third lumbar vertebra is a common cause of lumbago and sciatica It is manifested by localized soreness, distention and pain on unilateral or bilateral aspect of the third lumbar transverse process. There is also fixed tenderness point at the tip of the transverse process. This condition frequently occurs in young adults who are engaged in physical work. In recent years, the author used green tortoise probing cave method and stuck needle method for treating 72 cases of transverse process syndrome of the third lumbar vertebra, it is now report as follows.展开更多
A new classification of path-delay fault testability in a combinational circuit is presented in terms of testability of stuck-at faults in an equivalent circuit. Earlier results describing correlation of path-delay an...A new classification of path-delay fault testability in a combinational circuit is presented in terms of testability of stuck-at faults in an equivalent circuit. Earlier results describing correlation of path-delay and stuck-at faults are either incomplete, or use a complex model of equivalent circuit based on timing parameters. It is shown here that a path-delay fault (rising or falling) is testable if and only if certain single or multiple stuck-at fault in the equivalent circuit is testable. Thus, all aspects of path-delay faults related to testability under various classification schemes can be interpreted using the stuck-at fault model alone. The results unify most of the existing concepts and provide a better understanding of path-delay faults in logic circuits. Keywords delay fault - false path - redundancy - stuck-at fault Regular PaperThis work was funded in part by Motorola India Electronics Ltd., Bangalore 560042, India.An earlier version of this paper appeared in the Proceedings of the 12th Int. Coaf. VLSI Design, Jan. 1999.Subhashis Majumder is a professor and course leader for the Computer Science and Engineering Department of International Institute of Information Technology, Kolkata. He started his career in Texas Instruments India Pvt. Ltd. and has over seven years of industry experience. He received his M. Tech degree in computer science from the Indian Statistical Institute, Kolkata in 1996. His undergraduate work was done in the Electronics and Telecommunication Engineering Dept. of the Jadvpur University, Koikata. He also worked as a research assistant in the Computer Eng. Dept. of Rutgers University for a year. He has led product development teams working on protocol stack development as well as VoIP. His current areas of interest include delay fault testing, wire routing, partitioning, approximation algorithms, and application of computational geometry to CAD problems.Bhargab B. Bhattacharya received the B.Sc. degree in physics from the Presidency College, Calcutta, the B.Tech. and M.Tech. degrees in radiophysics and electronics, and the Ph.D. degree in computer science all from the University of Calcutta, India. Since 1982, he has been on the faculty of the Indian Statistical Institute, Calcutta, where currently he is a full professor. He visited the Department of Computer Science and Engineering, University of Nebraska-Lincoln, USA, during 1985–1987, and 2001–2002, and the Fault-Tolerant Computing Group, Institute of Informatics, at the University of Potsdam, Germany during 1998–2000. His research interest includes logic synthesis and testing of VLSI circuits, physical design, graph algorithms, and image processing architecture. He has published more than 130 papers in archival journals and refereed conference proceedings, and holds 6 United States patents. Currently, he is collaborating with Intel Corporation, USA, and IRISA, France, for development of image processing hardware and reconfigurable parallel computing tools. Dr. Bhattacharya is a fellow of the Indian National Academy of Engineering. He served on the conference committees of the International Test Conference (ITC), the Asian Test Symposium (ATS), the VLSI Design and Test Workshop (VDAT), the International Conference on Advanced Computing (ADCOMP), and the International Conference on High-Performance Computing (HiPC). For the International Conference on VLSI Design, he served as Tutorial Co-Chair (1994), Program Co-Chair (1997), General Co-Chair (2000), and as a member of the Steering Committee during 2001–2003. He is on the editorial board of the Journal of Circuits, Systems, and Computers (World Scientific, Singapore), and the Journal of Electronic Testing: Theory and Applications (Kluwer Academic Publishers, USA). [http://www.isical.ac.in/~bhargab]Vishwani D. Agrawal is the James J. Danaher Professor of Electrical and Computer Engineering at Auburn University, Alabama. He has over thirty years of industry and University experience, working at Bell Labs, Murray Hill, NJ; Rutgers University, New Brunswick, NJ; TRW, Redondo Beach, CA; IIT, Delhi, India; EG&G, Albuquerque. NM; and ATI, Champaign, IL. His areas of work include VLSI testing, lowpower design, and microwave antennas. He obtained his B.E. degree from the University of Roorkee (renamed as Indian Institute of Technology, Roorkee), India, in 1964; M.E. degree from the Indian Institute of Science, Bangalore, India, in 1966; and Ph.D. degree in electrical engineering from the University of Illinois, Urbana-Champaign, in 1971. He has published over 250 papers, has coauthored five books and holds thirteen United States patents. His textbook, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits (Kluwer Academic Publishers), co-authored with M. L. Bushnell, was published in 2000. He is the founder and Editor-in-Chief (1990-) of the Journal of Electronic Testing: Theory and Applications, and a past Editor-in-Chief (1985–87) of the IEEE Design & Test of Computers magazine. He is the Founder and Consulting Editor of the Frontiers in Electronic Testing Book Series of Kluwer Academic Publishers, Boston. He is a co-founder of the International Conference on VLSI Design, and the International Workshops on VLSI Design and Test, held annually in India. He has served on numerous conference committees and is a frequently invited speaker. He was the invited Plenary Speaker at the 1998 International Test Conference, Washington D.C., and the Keynote Speaker at the Ninth Asian Test Symposium in December 2000. During 1989 and 1990, he served on the Board of Governors of the IEEE Computer Society, and in 1994, chaired the Fellow Selection Committee of that Society. He has received seven Best Paper Awards and one Honorable Mention Paper Award. In 1998, he received the Harry H. Goode Memorial Award of the IEEE Computer Society, for innovative contributions to the field of electronic testing, and in 1993, received the Distinguished Alumnus Award of the University of Illinois at Urbana-Champaign, in recognition of his outstanding contributions in design and test of VLSI systems. Dr. Agrawal is a fellow of the IEEE, the ACM, and IETE-India. He has served on the advisory boards of the ECE Departments at University of Illinois, New Jersey Institute of Technology, and the City College of the City University of New York. [http://www.ece.wisc.edu/~va]Michael L. Bushnell is a professor and a Board of Trustees Research Fellow in the Electrical and Computer Engineering Department at Rutgers University, New Jersey. He was also a Henry Rutgers Research Fellow. He has 24 years of industry and university experience, working at General Electric, Honeywell, Instron, Applicon, and Rutgers University. He received his Ph.D. degree in 1986 and his M.S. degree in 1983, both from Carnegie Mellon University. His undergraduate work was done at the Massachusetts Institute of Technology. He is a Presidential Young Investigator (1990) of the National Science Foundation of the United States. He is a co-author of 4 books (including the leading VLSI testing textbook entitled Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits (Kluwer Academic Publishers, 2000), co-authored with Vishwani Agrawal), 91 papers, and 7 patents. He is the co-author of two Prize Papers and one Honorable Mention paper. He served twice as Program Co-Chair of the International Conference on VLSI Design (1995 and 1996), and twice as the Conference Vice-Chair of the North Atlantic Test Workshop (2002 and 2003). His current VLSI CAD research interests are automatic mixed-signal circuit test-pattern generation, built-in self-testing, synthesis for testability, fault modeling for nano-technology, and low-power design. [http://www.ece.rutgers.edu/directory/bushnell.html]展开更多
This paper presents a built-in self-test (BIST) scheme for detecting allrobustly testable multiple stuck-open faults confined to any single complex cell of a CMOS circuit.The test pattern generator (TPG) generates all...This paper presents a built-in self-test (BIST) scheme for detecting allrobustly testable multiple stuck-open faults confined to any single complex cell of a CMOS circuit.The test pattern generator (TPG) generates all n·2~n single-input-change (SIC) ordered test pairsfor an n-input circuit-under-test (CUT) contained in a sequence of length 2n·2~n. The proposeddesign is universal, i.e., independent of the structure and functionality of the CUT. A counter thatcounts the number of alternate transitions at the output of the CUT, is used as a signatureanalyzer (SA). The design of TPG and SA is simple and no special design-or synthesis-for-testabilitytechniques and/or additional control lines are needed.展开更多
This paper addresses the fault detection(FD)problem for discretetime sector-bounded non-linear systems with finite-frequency servo inputs.The non-linear systems are firstly modelled as multi-models.The main contributi...This paper addresses the fault detection(FD)problem for discretetime sector-bounded non-linear systems with finite-frequency servo inputs.The non-linear systems are firstly modelled as multi-models.The main contributions are that a novel FD filter which combines the finite-frequency H∞and H−indices is designed.Different from the existing methods,the proposed FD scheme guarantees that the generated residuals are robust against the servo inputs in fault-free case and sensitive to them in faulty cases.Thus,the small sensor stuck faults including outagefaults can be detected.For this class of systems,the existing finite-frequency FD filter design methods are invalid.A new lemma is developed to characterise the system performances in finite-frequency domain.In addition,sufficient conditions for the existence of such a FD filter are derived by introducing slack variable and linear matrix inequalities techniques.Finally,an example is presented to demonstrate the method and its effectiveness.展开更多
基金National Natural Science Foundation of China(61004072)Fundamental Research Funds for the Central Universities(HIT.NSRIF.2009003)+1 种基金Research Fund for the Doctoral Program of Higher Education of China (20070213061, 20102302110031)Scientific Research Foundation for the Returned Overseas Chinese Scholars of Harbin (2010RFLXG001)
文摘A fault tolerant control （FTC） design technique against actuator stuck faults is investigated using integral-type sliding mode control （ISMC） with application to spacecraft attitude maneuvering control system. The principle of the proposed FTC scheme is to design an integral-type sliding mode attitude controller using on-line parameter adaptive updating law to compensate for the effects of stuck actuators. This adaptive law also provides both the estimates of the system parameters and external disturbances such that a prior knowledge of the spacecraft inertia or boundedness of disturbances is not required. Moreover, by including the integral feedback term, the designed controller can not only tolerate actuator stuck faults, but also compensate the disturbances with constant components. For the synthesis of controller, the fault time, patterns and values are unknown in advance, as motivated from a practical spacecraft control application. Complete stability and performance analysis are presented and illustrative simulation results of application to a spacecraft show that high precise attitude control with zero steady-error is successfully achieved using various scenarios of stuck failures in actuators.
文摘A nonlinear robust trajectory tracking strategy for a gliding hypersonic vehicle with an aileron stuck at an unknown position is presented in this paper. First, the components of translational motion dynamics perpendicular to the velocity are derived, and then a guidance law based on a time-varying sliding mode method is used to realize trajectory tracking. Furthermore, the rotational equations of motion are separated into an actuated subsystem and an unactuated subsystem. And an adaptive time-varying sliding mode attitude controller is proposed based on the actuated subsystem to track the command attitude and the tracking performance and robustness are therefore enhanced. The proposed guidance law and attitude controller make the hypersonic vehicle fly along the reference trajectory even when the aileron is stuck at an unknown angle. Finally, a hypersonic benchmark platform is used to demonstrate the effectiveness of the proposed strategy.
基金support from the national projects(Grant No.:2011ZX05009-005and2010CB226703)
文摘A stuck drill string results in a major non-productive cost in extended reach drilling engineering. The first step is to determine the depth at which the sticking has occurred. Methods of measurement have been proved useful for determining the stuck points, but these operations take considerable time. As a result of the limitation with the current operational practices, calculation methods are still preferred to estimate the stuck point depth. Current analytical methods do not consider friction and are only valid for vertical rather than extended reach wells. The numerical method is established to take full account of down hole friction, tool joint, upset end of drill pipe, combination drill strings and tubular materials so that it is valid to determine the stuck point in extended reach wells. The pull test, torsion test and combined test of rotation and pulling can be used to determine the stuck point. The results show that down hole friction, tool joint, upset end of drill pipe, tubular sizes and materials have significant effects on the pull length and/or the twist angle of the stuck drill string.
文摘According to New York Times on November 19, as retailers battle to draw customers into their stores on Black Friday, online merchants are plotting a cunning ambush, offering an arsenal of mobile-only deals intended to pick off shoppers as they wait in line. The Gilt Groupe, for example, which
文摘Transverse process syndrome of the third lumbar vertebra is a common cause of lumbago and sciatica It is manifested by localized soreness, distention and pain on unilateral or bilateral aspect of the third lumbar transverse process. There is also fixed tenderness point at the tip of the transverse process. This condition frequently occurs in young adults who are engaged in physical work. In recent years, the author used green tortoise probing cave method and stuck needle method for treating 72 cases of transverse process syndrome of the third lumbar vertebra, it is now report as follows.
文摘A new classification of path-delay fault testability in a combinational circuit is presented in terms of testability of stuck-at faults in an equivalent circuit. Earlier results describing correlation of path-delay and stuck-at faults are either incomplete, or use a complex model of equivalent circuit based on timing parameters. It is shown here that a path-delay fault (rising or falling) is testable if and only if certain single or multiple stuck-at fault in the equivalent circuit is testable. Thus, all aspects of path-delay faults related to testability under various classification schemes can be interpreted using the stuck-at fault model alone. The results unify most of the existing concepts and provide a better understanding of path-delay faults in logic circuits. Keywords delay fault - false path - redundancy - stuck-at fault Regular PaperThis work was funded in part by Motorola India Electronics Ltd., Bangalore 560042, India.An earlier version of this paper appeared in the Proceedings of the 12th Int. Coaf. VLSI Design, Jan. 1999.Subhashis Majumder is a professor and course leader for the Computer Science and Engineering Department of International Institute of Information Technology, Kolkata. He started his career in Texas Instruments India Pvt. Ltd. and has over seven years of industry experience. He received his M. Tech degree in computer science from the Indian Statistical Institute, Kolkata in 1996. His undergraduate work was done in the Electronics and Telecommunication Engineering Dept. of the Jadvpur University, Koikata. He also worked as a research assistant in the Computer Eng. Dept. of Rutgers University for a year. He has led product development teams working on protocol stack development as well as VoIP. His current areas of interest include delay fault testing, wire routing, partitioning, approximation algorithms, and application of computational geometry to CAD problems.Bhargab B. Bhattacharya received the B.Sc. degree in physics from the Presidency College, Calcutta, the B.Tech. and M.Tech. degrees in radiophysics and electronics, and the Ph.D. degree in computer science all from the University of Calcutta, India. Since 1982, he has been on the faculty of the Indian Statistical Institute, Calcutta, where currently he is a full professor. He visited the Department of Computer Science and Engineering, University of Nebraska-Lincoln, USA, during 1985–1987, and 2001–2002, and the Fault-Tolerant Computing Group, Institute of Informatics, at the University of Potsdam, Germany during 1998–2000. His research interest includes logic synthesis and testing of VLSI circuits, physical design, graph algorithms, and image processing architecture. He has published more than 130 papers in archival journals and refereed conference proceedings, and holds 6 United States patents. Currently, he is collaborating with Intel Corporation, USA, and IRISA, France, for development of image processing hardware and reconfigurable parallel computing tools. Dr. Bhattacharya is a fellow of the Indian National Academy of Engineering. He served on the conference committees of the International Test Conference (ITC), the Asian Test Symposium (ATS), the VLSI Design and Test Workshop (VDAT), the International Conference on Advanced Computing (ADCOMP), and the International Conference on High-Performance Computing (HiPC). For the International Conference on VLSI Design, he served as Tutorial Co-Chair (1994), Program Co-Chair (1997), General Co-Chair (2000), and as a member of the Steering Committee during 2001–2003. He is on the editorial board of the Journal of Circuits, Systems, and Computers (World Scientific, Singapore), and the Journal of Electronic Testing: Theory and Applications (Kluwer Academic Publishers, USA). [http://www.isical.ac.in/~bhargab]Vishwani D. Agrawal is the James J. Danaher Professor of Electrical and Computer Engineering at Auburn University, Alabama. He has over thirty years of industry and University experience, working at Bell Labs, Murray Hill, NJ; Rutgers University, New Brunswick, NJ; TRW, Redondo Beach, CA; IIT, Delhi, India; EG&G, Albuquerque. NM; and ATI, Champaign, IL. His areas of work include VLSI testing, lowpower design, and microwave antennas. He obtained his B.E. degree from the University of Roorkee (renamed as Indian Institute of Technology, Roorkee), India, in 1964; M.E. degree from the Indian Institute of Science, Bangalore, India, in 1966; and Ph.D. degree in electrical engineering from the University of Illinois, Urbana-Champaign, in 1971. He has published over 250 papers, has coauthored five books and holds thirteen United States patents. His textbook, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits (Kluwer Academic Publishers), co-authored with M. L. Bushnell, was published in 2000. He is the founder and Editor-in-Chief (1990-) of the Journal of Electronic Testing: Theory and Applications, and a past Editor-in-Chief (1985–87) of the IEEE Design & Test of Computers magazine. He is the Founder and Consulting Editor of the Frontiers in Electronic Testing Book Series of Kluwer Academic Publishers, Boston. He is a co-founder of the International Conference on VLSI Design, and the International Workshops on VLSI Design and Test, held annually in India. He has served on numerous conference committees and is a frequently invited speaker. He was the invited Plenary Speaker at the 1998 International Test Conference, Washington D.C., and the Keynote Speaker at the Ninth Asian Test Symposium in December 2000. During 1989 and 1990, he served on the Board of Governors of the IEEE Computer Society, and in 1994, chaired the Fellow Selection Committee of that Society. He has received seven Best Paper Awards and one Honorable Mention Paper Award. In 1998, he received the Harry H. Goode Memorial Award of the IEEE Computer Society, for innovative contributions to the field of electronic testing, and in 1993, received the Distinguished Alumnus Award of the University of Illinois at Urbana-Champaign, in recognition of his outstanding contributions in design and test of VLSI systems. Dr. Agrawal is a fellow of the IEEE, the ACM, and IETE-India. He has served on the advisory boards of the ECE Departments at University of Illinois, New Jersey Institute of Technology, and the City College of the City University of New York. [http://www.ece.wisc.edu/~va]Michael L. Bushnell is a professor and a Board of Trustees Research Fellow in the Electrical and Computer Engineering Department at Rutgers University, New Jersey. He was also a Henry Rutgers Research Fellow. He has 24 years of industry and university experience, working at General Electric, Honeywell, Instron, Applicon, and Rutgers University. He received his Ph.D. degree in 1986 and his M.S. degree in 1983, both from Carnegie Mellon University. His undergraduate work was done at the Massachusetts Institute of Technology. He is a Presidential Young Investigator (1990) of the National Science Foundation of the United States. He is a co-author of 4 books (including the leading VLSI testing textbook entitled Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits (Kluwer Academic Publishers, 2000), co-authored with Vishwani Agrawal), 91 papers, and 7 patents. He is the co-author of two Prize Papers and one Honorable Mention paper. He served twice as Program Co-Chair of the International Conference on VLSI Design (1995 and 1996), and twice as the Conference Vice-Chair of the North Atlantic Test Workshop (2002 and 2003). His current VLSI CAD research interests are automatic mixed-signal circuit test-pattern generation, built-in self-testing, synthesis for testability, fault modeling for nano-technology, and low-power design. [http://www.ece.rutgers.edu/directory/bushnell.html]
文摘This paper presents a built-in self-test (BIST) scheme for detecting allrobustly testable multiple stuck-open faults confined to any single complex cell of a CMOS circuit.The test pattern generator (TPG) generates all n·2~n single-input-change (SIC) ordered test pairsfor an n-input circuit-under-test (CUT) contained in a sequence of length 2n·2~n. The proposeddesign is universal, i.e., independent of the structure and functionality of the CUT. A counter thatcounts the number of alternate transitions at the output of the CUT, is used as a signatureanalyzer (SA). The design of TPG and SA is simple and no special design-or synthesis-for-testabilitytechniques and/or additional control lines are needed.
基金This work was supported in part by the Funds of the National Natural Science Foundation of China[grant number 61621004],[grant number 61420106016]the Research Fund of State Key Laboratory of Synthetical Automation for Process Industries[grant number 2013ZCX01].
文摘This paper addresses the fault detection(FD)problem for discretetime sector-bounded non-linear systems with finite-frequency servo inputs.The non-linear systems are firstly modelled as multi-models.The main contributions are that a novel FD filter which combines the finite-frequency H∞and H−indices is designed.Different from the existing methods,the proposed FD scheme guarantees that the generated residuals are robust against the servo inputs in fault-free case and sensitive to them in faulty cases.Thus,the small sensor stuck faults including outagefaults can be detected.For this class of systems,the existing finite-frequency FD filter design methods are invalid.A new lemma is developed to characterise the system performances in finite-frequency domain.In addition,sufficient conditions for the existence of such a FD filter are derived by introducing slack variable and linear matrix inequalities techniques.Finally,an example is presented to demonstrate the method and its effectiveness.
