Strained-Si pMOSFETs on very thin relaxed virtua l SiGe substrates are presented.The 240nm relaxed virtual Si 0.8 Ge 0.2 layer on 100nm low-temperature Si(LT-Si) is grown on Si(100) substrates by molecular be...Strained-Si pMOSFETs on very thin relaxed virtua l SiGe substrates are presented.The 240nm relaxed virtual Si 0.8 Ge 0.2 layer on 100nm low-temperature Si(LT-Si) is grown on Si(100) substrates by molecular beam epitaxy.LT-Si buffer layer is used to release stress of the SiGe layer so as to make it relaxed.DCXRD,AFM,and TEM measurements indicate that the strain relaxed degree of SiGe layer is 85%,RMS roughness is 1.02nm,and threading dislocation density is at most 107cm -2 .At room temperature,a maximum hole mobility of strained-Si pMOSFET is 140cm2/(V·s).Device performance is comparable to that of devices achieved on several microns thick relaxed virtual SiGe substrates.展开更多
基于SiGe合金的电子器件具有广阔的空间应用前景,但是也受到空间环境中粒子辐照损伤的威胁.本文通过蒙特卡罗模拟研究了1—1000 Me V质子对SiGe合金和SiGe/Si异质结构造成的位移损伤.结果表明,低能质子(1—100 Me V)在SiGe合金中主要通...基于SiGe合金的电子器件具有广阔的空间应用前景,但是也受到空间环境中粒子辐照损伤的威胁.本文通过蒙特卡罗模拟研究了1—1000 Me V质子对SiGe合金和SiGe/Si异质结构造成的位移损伤.结果表明,低能质子(1—100 Me V)在SiGe合金中主要通过库仑散射和弹性碰撞产生Si初级离位原子(primary knock-on atom,PKA)和Ge PKA,损伤能分布在质子射程末端形成一个明显的布拉格峰,而高能质子(300—1000 Me V)在SiGe合金中的非弹性碰撞更加显著,出现更多的PKA类型,损伤能主要分布在质子射程前端.同时,质子在SiGe/Si异质结构中的损伤能随质子能量的增大呈现出整体下降的趋势,反向入射质子(10 Me V和100 Me V)比正向入射质子在界面处Si基底一侧产生的损伤能更大,导致界面两侧的损伤能起伏更为剧烈,可能造成更加严重的位移损伤.此外,Ge含量会影响质子在SiGe合金中的PKA类型、损伤能分布和非电离能量损失,随着Ge含量的增大,高能质子在SiGe合金中的非电离能量损失逐渐变大,但是,Ge含量对质子在小尺寸SiGe/Si异质结构中总损伤能的影响不显著.总体上,这项工作说明了质子在SiGe合金和SiGe/Si异质结构中产生的位移损伤和质子能量密切相关,低能质子倾向于产生更多的自反冲原子,并在小尺寸SiGe/Si异质结构中产生位移损伤,为SiGe合金基电子器件的位移损伤效应研究和抗辐照加固技术提供了数据支持.展开更多
In the ultra-thin relaxed SiGe virtual substrates, a strained-Si channel p-type Metal Oxide Semiconductor Field Effect Transistor (p-MOSFET) is presented. Built on strained-Si/240nm relaxed-Si0.8 Ge0.2/ 100nm Low Temp...In the ultra-thin relaxed SiGe virtual substrates, a strained-Si channel p-type Metal Oxide Semiconductor Field Effect Transistor (p-MOSFET) is presented. Built on strained-Si/240nm relaxed-Si0.8 Ge0.2/ 100nm Low Temperature Si (LT-Si)/10nm Si buffer was grown by Molecular Beam Epitaxy (MBE), in which LT-Si layer is used to release stress of the SiGe layer and made it relaxed. Measurement indicates that the strained-Si p-MOSFET's (L=4.2μm) transconductance and the hole mobility are enhanced 30% and 50% respectively, compared with that of conventional bulk-Si. The maximum hole mobility for strained-Si device is 140cm2/Vs. The device performance is comparable to devices achieved on several μm thick composition graded buffers and relaxed-SiGe layer virtual substrates.展开更多
The effect of substrate doping on the threshold voltages of buried channel pMOSFET based on strained-SiGe technology was studied.By physically deriving the models of the threshold voltages,it is found that the layer w...The effect of substrate doping on the threshold voltages of buried channel pMOSFET based on strained-SiGe technology was studied.By physically deriving the models of the threshold voltages,it is found that the layer which inversely occurs first is substrate doping dependent,giving explanation for the variation of plateau observed in the C-V characteristics of this device,as the doping concentration increases.The threshold voltages obtained from the proposed model are-1.2805 V for buried channel and-2.9358 V for surface channel at a lightly doping case,and-3.41 V for surface channel at a heavily doping case,which agrees well with the experimental results.Also,the variations of the threshold voltages with several device parameters are discussed,which provides valuable reference to the designers of strained-SiGe devices.展开更多
In this paper,a high-gain inductorless LNA(low-noise amplifier)compatible with multiple communication protocols from 0.1 to 5.1 GHz is proposed.A composite resistor-capacitor feedback structure is employed to achieve ...In this paper,a high-gain inductorless LNA(low-noise amplifier)compatible with multiple communication protocols from 0.1 to 5.1 GHz is proposed.A composite resistor-capacitor feedback structure is employed to achieve a wide bandwidth matching range and good gain flatness.A second stage with a Darlington pair is used to increase the overall gain of the amplifier,while the gain of the first stage is reduced to reduce the overall noise.The amplifier is based on a 0.25μm SiGe BiCMOS process,and thanks to the inductorless circuit structure,the core circuit area is only 0.03 mm^(2).Test results show that the lowest noise figure(NF)in the operating band is 1.99 dB,the power gain reaches 29.7 dB,the S_(11)and S_(22)are less than-10 dB,the S_(12)is less than-30 dB,the IIP3 is 0.81dBm,and the OP_(1dB)is 10.27 dBm.The operating current is 31.18 mA at 3.8 V supply.展开更多
文摘Strained-Si pMOSFETs on very thin relaxed virtua l SiGe substrates are presented.The 240nm relaxed virtual Si 0.8 Ge 0.2 layer on 100nm low-temperature Si(LT-Si) is grown on Si(100) substrates by molecular beam epitaxy.LT-Si buffer layer is used to release stress of the SiGe layer so as to make it relaxed.DCXRD,AFM,and TEM measurements indicate that the strain relaxed degree of SiGe layer is 85%,RMS roughness is 1.02nm,and threading dislocation density is at most 107cm -2 .At room temperature,a maximum hole mobility of strained-Si pMOSFET is 140cm2/(V·s).Device performance is comparable to that of devices achieved on several microns thick relaxed virtual SiGe substrates.
文摘基于SiGe合金的电子器件具有广阔的空间应用前景,但是也受到空间环境中粒子辐照损伤的威胁.本文通过蒙特卡罗模拟研究了1—1000 Me V质子对SiGe合金和SiGe/Si异质结构造成的位移损伤.结果表明,低能质子(1—100 Me V)在SiGe合金中主要通过库仑散射和弹性碰撞产生Si初级离位原子(primary knock-on atom,PKA)和Ge PKA,损伤能分布在质子射程末端形成一个明显的布拉格峰,而高能质子(300—1000 Me V)在SiGe合金中的非弹性碰撞更加显著,出现更多的PKA类型,损伤能主要分布在质子射程前端.同时,质子在SiGe/Si异质结构中的损伤能随质子能量的增大呈现出整体下降的趋势,反向入射质子(10 Me V和100 Me V)比正向入射质子在界面处Si基底一侧产生的损伤能更大,导致界面两侧的损伤能起伏更为剧烈,可能造成更加严重的位移损伤.此外,Ge含量会影响质子在SiGe合金中的PKA类型、损伤能分布和非电离能量损失,随着Ge含量的增大,高能质子在SiGe合金中的非电离能量损失逐渐变大,但是,Ge含量对质子在小尺寸SiGe/Si异质结构中总损伤能的影响不显著.总体上,这项工作说明了质子在SiGe合金和SiGe/Si异质结构中产生的位移损伤和质子能量密切相关,低能质子倾向于产生更多的自反冲原子,并在小尺寸SiGe/Si异质结构中产生位移损伤,为SiGe合金基电子器件的位移损伤效应研究和抗辐照加固技术提供了数据支持.
文摘In the ultra-thin relaxed SiGe virtual substrates, a strained-Si channel p-type Metal Oxide Semiconductor Field Effect Transistor (p-MOSFET) is presented. Built on strained-Si/240nm relaxed-Si0.8 Ge0.2/ 100nm Low Temperature Si (LT-Si)/10nm Si buffer was grown by Molecular Beam Epitaxy (MBE), in which LT-Si layer is used to release stress of the SiGe layer and made it relaxed. Measurement indicates that the strained-Si p-MOSFET's (L=4.2μm) transconductance and the hole mobility are enhanced 30% and 50% respectively, compared with that of conventional bulk-Si. The maximum hole mobility for strained-Si device is 140cm2/Vs. The device performance is comparable to devices achieved on several μm thick composition graded buffers and relaxed-SiGe layer virtual substrates.
基金Projects(51308040203,6139801)supported by the National Ministries and CommissionsProjects(72105499,72104089)supported the Fundamental Research Funds for the Central Universities,ChinaProject(2010JQ8008)supported by the Natural Science Basic Research Plan in Shaanxi Province,China
文摘The effect of substrate doping on the threshold voltages of buried channel pMOSFET based on strained-SiGe technology was studied.By physically deriving the models of the threshold voltages,it is found that the layer which inversely occurs first is substrate doping dependent,giving explanation for the variation of plateau observed in the C-V characteristics of this device,as the doping concentration increases.The threshold voltages obtained from the proposed model are-1.2805 V for buried channel and-2.9358 V for surface channel at a lightly doping case,and-3.41 V for surface channel at a heavily doping case,which agrees well with the experimental results.Also,the variations of the threshold voltages with several device parameters are discussed,which provides valuable reference to the designers of strained-SiGe devices.
基金funded by the Science,Technology and Innovation Commission of Shenzhen Municipality(JCYJ20220818101001003)。
文摘In this paper,a high-gain inductorless LNA(low-noise amplifier)compatible with multiple communication protocols from 0.1 to 5.1 GHz is proposed.A composite resistor-capacitor feedback structure is employed to achieve a wide bandwidth matching range and good gain flatness.A second stage with a Darlington pair is used to increase the overall gain of the amplifier,while the gain of the first stage is reduced to reduce the overall noise.The amplifier is based on a 0.25μm SiGe BiCMOS process,and thanks to the inductorless circuit structure,the core circuit area is only 0.03 mm^(2).Test results show that the lowest noise figure(NF)in the operating band is 1.99 dB,the power gain reaches 29.7 dB,the S_(11)and S_(22)are less than-10 dB,the S_(12)is less than-30 dB,the IIP3 is 0.81dBm,and the OP_(1dB)is 10.27 dBm.The operating current is 31.18 mA at 3.8 V supply.
