Uniform memory multicore neural network accelerators(UNNAs)furnish huge computing power to emerging neural network applications.Meanwhile,with neural network architectures going deeper and wider,the limited memory cap...Uniform memory multicore neural network accelerators(UNNAs)furnish huge computing power to emerging neural network applications.Meanwhile,with neural network architectures going deeper and wider,the limited memory capacity has become a constraint to deploy models on UNNA platforms.Therefore how to efficiently manage memory space and how to reduce workload footprints are urgently significant.In this paper,we propose Tetris:a heuristic static memory management framework for UNNA platforms.Tetris reconstructs execution flows and synchronization relationships among cores to analyze each tensor’s liveness interval.Then the memory management problem is converted to a sequence permutation problem.Tetris uses a genetic algorithm to explore the permutation space to optimize the memory management strategy and reduce memory footprints.We evaluate several typical neural networks and the experimental results demonstrate that Tetris outperforms the state-of-the-art memory allocation methods,and achieves an average memory reduction ratio of 91.9%and 87.9%for a quad-core and a 16-core Cambricon-X platform,respectively.展开更多
Using computer-aided design three-dimensional （3D） simulation technology, the recovery mechanism of single event upset and the effects of spacing and hit angle on the recovery are studied. It is found that the multi...Using computer-aided design three-dimensional （3D） simulation technology, the recovery mechanism of single event upset and the effects of spacing and hit angle on the recovery are studied. It is found that the multi-node charge collection plays a key role in recovery and shielding the charge sharing by adding guard rings. It cannot exhibit the recovery effect. It is also indicated that the upset linear energy transfer （LET） threshold is kept constant while the recovery LET threshold increases as the spacing increases. Additionally, the effect of incident angle on recovery is analysed and it is shown that a larger angle can bring about a stronger charge sharing effect, thus strengthening the recovery ability.展开更多
Synergistic effects of the total ionizing dose （TID） on the single event upset （SEU） sensitivity in static random access memories （SRAMs） were studied by using protons. The total dose was cumulated with high flu...Synergistic effects of the total ionizing dose （TID） on the single event upset （SEU） sensitivity in static random access memories （SRAMs） were studied by using protons. The total dose was cumulated with high flux protons during the TID exposure, and the SEU cross section was tested with low flux protons at several cumulated dose steps. Because of the radiation-induced off-state leakage current increase of the CMOS transistors, the noise margin became asymmetric and the memory imprint effect was observed.展开更多
This paper explores the impact of back-gate bias (V_(soi)) and supply voltage (V_(DD)) on the single-event upset (SEU) cross section of 0.18μm configurable silicon-on-insulator static random-access memory (SRAM) unde...This paper explores the impact of back-gate bias (V_(soi)) and supply voltage (V_(DD)) on the single-event upset (SEU) cross section of 0.18μm configurable silicon-on-insulator static random-access memory (SRAM) under high linear energy transfer heavyion experimentation.The experimental findings demonstrate that applying a negative back-gate bias to NMOS and a positive back-gate bias to PMOS enhances the SEU resistance of SRAM.Specifically,as the back-gate bias for N-type transistors(V_(nsoi)) decreases from 0 to-10 V,the SEU cross section decreases by 93.23%,whereas an increase in the back-gate bias for P-type transistors (V_(psoi)) from 0 to 10 V correlates with an 83.7%reduction in SEU cross section.Furthermore,a significant increase in the SEU cross section was observed with increase in supply voltage,as evidenced by a 159%surge at V_(DD)=1.98 V compared with the nominal voltage of 1.8 V.To explore the physical mechanisms underlying these experimental data,we analyzed the dependence of the critical charge of the circuit and the collected charge on the bias voltage by simulating SEUs using technology computer-aided design.展开更多
In recent years,carbon nanotube field effect transistor(CNTFET)has become an attractive alternative to silicon for designing high-performance,highly stable,and low-power static random access memory(SRAM).SRAM serves a...In recent years,carbon nanotube field effect transistor(CNTFET)has become an attractive alternative to silicon for designing high-performance,highly stable,and low-power static random access memory(SRAM).SRAM serves as a cache memory in computers and many portable devices.Carbon nanotubes(CNTs),because of their exceptional transport capabilities,outstanding thermal conductivities,and impressive current handling capacities,have demonstrated great potential as an alternative device to the standard complementary metal-oxide-semiconductor(CMOS).The SRAM cell design using CNTFET is being compared to SRAM cell designs built using traditional CMOS technology.This paper presents the comprehensive analysis of CMOS&CNTFET based 8T SRAM cell design.Because of the nanoscale size,ballistic transport,and higher carrier mobility of the semiconducting nanotubes in CNTFET,it is integrated into the 8T SRAM cell.The approach incorporates several nonidealities,including the presence of quantum confinement consequences in the peripheral and transverse prescriptions,acoustic and transparent photon diffraction in the region surrounding the channel,as well as the screening effects by parallel CNTs in CNTFETs with multiple CNTs.By incorporating Stanford University CNTFET model in CADENCE(virtuoso)32 nm simulation,we have found that CNTFET SRAM cell is 4 times faster in terms of write/read delay and the write/read power delay product(PDP)value is almost 5 times lower compared to CMOS based SRAM.We have also analyzed the effect of temperature&different tube positions of CNTs on the performance evaluation of the 8T SRAM cell.展开更多
Artificial intelligence(AI)processes data-centric applications with minimal effort.However,it poses new challenges to system design in terms of computational speed and energy efficiency.The traditional von Neumann arc...Artificial intelligence(AI)processes data-centric applications with minimal effort.However,it poses new challenges to system design in terms of computational speed and energy efficiency.The traditional von Neumann architecture cannot meet the requirements of heavily datacentric applications due to the separation of computation and storage.The emergence of computing inmemory(CIM)is significant in circumventing the von Neumann bottleneck.A commercialized memory architecture,static random-access memory(SRAM),is fast and robust,consumes less power,and is compatible with state-of-the-art technology.This study investigates the research progress of SRAM-based CIM technology in three levels:circuit,function,and application.It also outlines the problems,challenges,and prospects of SRAM-based CIM macros.展开更多
Pattem imprinting in deep sub-micron static random access memories （SRAMs） during total dose irradiation is inves- tigated in detail. As the dose accumulates, the data pattern of memory cells loading during irradiat...Pattem imprinting in deep sub-micron static random access memories （SRAMs） during total dose irradiation is inves- tigated in detail. As the dose accumulates, the data pattern of memory cells loading during irradiation is gradually imprinted on their background data pattern. We build a relationship between the memory cell＇s static noise margin （SNM） and the background data, and study the influence of irradiation on the probability density function of ASNM, which is the difference between two data sides＇ SNMs, to discuss the reason for pattern imprinting. Finally, we demonstrate that, for micron and deep sub-micron devices, the mechanism of pattern imprinting is the bias-dependent threshold shift of the transistor, but for a deep sub-micron device the shift results from charge trapping in the shallow trench isolation （STI） oxide rather than from the gate oxide of the micron-device.展开更多
In this work, the total ionizing dose（TID） effect on 130 nm partially depleted（PD） silicon-on-insulator（SOI） static random access memory（SRAM） cell stability is measured. The SRAM cell test structure allowing ...In this work, the total ionizing dose（TID） effect on 130 nm partially depleted（PD） silicon-on-insulator（SOI） static random access memory（SRAM） cell stability is measured. The SRAM cell test structure allowing direct measurement of the static noise margin（SNM） is specifically designed and irradiated by gamma-ray. Both data sides＇ SNM of 130 nm PD SOI SRAM cell are decreased by TID, which is different from the conclusion obtained in old generation devices that one data side＇s SNM is decreased and the other data side＇s SNM is increased. Moreover, measurement of SNM under different supply voltages（Vdd） reveals that SNM is more sensitive to TID under lower Vdd. The impact of TID on SNM under data retention Vddshould be tested, because Vddof SRAM cell under data retention mode is lower than normal Vdd.The mechanism under the above results is analyzed by measurement of I–V characteristics of SRAM cell transistors.展开更多
The 28 nm process has a high cost-performance ratio and has gradually become the standard for the field of radiation-hardened devices.However,owing to the minimum physical gate length of only 35 nm,the physical area o...The 28 nm process has a high cost-performance ratio and has gradually become the standard for the field of radiation-hardened devices.However,owing to the minimum physical gate length of only 35 nm,the physical area of a standard 6T SRAM unit is approximately 0.16μm^(2),resulting in a significant enhancement of multi-cell charge-sharing effects.Multiple-cell upsets(MCUs)have become the primary physical mechanism behind single-event upsets(SEUs)in advanced nanometer node devices.The range of ionization track effects increases with higher ion energies,and spacecraft in orbit primarily experience SEUs caused by high-energy ions.However,ground accelerator experiments have mainly obtained low-energy ion irradiation data.Therefore,the impact of ion energy on the SEU cross section,charge collection mechanisms,and MCU patterns and quantities in advanced nanometer devices remains unclear.In this study,based on the experimental platform of the Heavy Ion Research Facility in Lanzhou,low-and high-energy heavy-ion beams were used to study the SEUs of 28 nm SRAM devices.The influence of ion energy on the charge collection processes of small-sensitive-volume devices,MCU patterns,and upset cross sections was obtained,and the applicable range of the inverse cosine law was clarified.The findings of this study are an important guide for the accurate evaluation of SEUs in advanced nanometer devices and for the development of radiation-hardening techniques.展开更多
A dual double interlocked storage cell(DICE)interleaving layout static random-access memory(SRAM)is designed and manufactured based on 65 nm bulk complementary metal oxide semiconductor technology.The single event ups...A dual double interlocked storage cell(DICE)interleaving layout static random-access memory(SRAM)is designed and manufactured based on 65 nm bulk complementary metal oxide semiconductor technology.The single event upset(SEU)cross sections of this memory are obtained via heavy ion irradiation with a linear energy transfer(LET)value ranging from 1.7 to 83.4 MeV/(mg/cm^(2)).Experimental results show that the upset threshold(LETth)of a 4 KB block is approximately 6 MeV/(mg/cm^(2)),which is much better than that of a standard unhardened SRAM with an identical technology node.A 1 KB block has a higher LETth of 25 MeV/(mg/cm^(2))owing to the use of the error detection and correction(EDAC)code.For a Ta ion irradiation test with the highest LET value(83.4 MeV/(mg/cm^(2))),the benefit of the EDAC code is reduced significantly because the multi-bit upset proportion in the SEU is increased remarkably.Compared with normal incident ions,the memory exhibits a higher SEU sensitivity in the tilt angle irradiation test.Moreover,the SEU cross section indicates a significant dependence on the data pattern.When comprehensively considering HSPICE simulation results and the sensitive area distributions of the DICE cell,it is shown that the data pattern dependence is primarily associated with the arrangement of sensitive transistor pairs in the layout.Finally,some suggestions are provided to further improve the radiation resistance of the memory.By implementing a particular design at the layout level,the SEU tolerance of the memory is improved significantly at a low area cost.Therefore,the designed 65 nm SRAM is suitable for electronic systems operating in serious radiation environments.展开更多
To predict the soft error rate for applications, it is essential to study the energy dependence of the single-event-upset(SEU) cross-section. In this work, we present a direct measurement of the SEU cross-section with...To predict the soft error rate for applications, it is essential to study the energy dependence of the single-event-upset(SEU) cross-section. In this work, we present a direct measurement of the SEU cross-section with the Back-n white neutron source at the China Spallation Neutron Source. The measured cross section is consistent with the soft error data from the manufacturer and the result suggests that the threshold energy of the SEU is about 0.5 Me V, which confirms the statement in Iwashita’s report that the threshold energy for neutron soft error is much below that of the(n, α) cross-section of silicon.In addition, an index of the effective neutron energy is suggested to characterize the similarity between a spallation neutron beam and the standard atmospheric neutron environment.展开更多
This paper develops a new simulation technique to characterize single event effects on semiconductor devices. The technique used to calculate the single event effects is developed according to the physical interaction...This paper develops a new simulation technique to characterize single event effects on semiconductor devices. The technique used to calculate the single event effects is developed according to the physical interaction mechanism of a single event effect. An application of the first principles simulation technique is performed to predict the ground-test single event upset effect on field-programmable gate arrays based on 0.25μm advanced complementary metal-oxidesemiconductor technology. The agreement between the single event upset cross section accessed from a broad-beam heavy ion experiment and simulation shows that the simulation technique could be used to characterize the single event effects induced by heavy ions on a semiconductor device.展开更多
The pattern dependence in synergistic effects was studied in a 0.18 μm static random access memory（SRAM） circuit.Experiments were performed under two SEU test environments：3 Me V protons and heavy ions.Measured re...The pattern dependence in synergistic effects was studied in a 0.18 μm static random access memory（SRAM） circuit.Experiments were performed under two SEU test environments：3 Me V protons and heavy ions.Measured results show different trends.In heavy ion SEU test,the degradation in the peripheral circuitry also existed because the measured SEU cross section decreased regardless of the patterns written to the SRAM array.TCAD simulation was performed.TIDinduced degradation in n MOSFETs mainly induced the imprint effect in the SRAM cell,which is consistent with the measured results under the proton environment,but cannot explain the phenomena observed under heavy ion environment.A possible explanation could be the contribution from the radiation-induced GIDL in pMOSFETs.展开更多
An approach to design small scale CMOS static random access memory (SRAM) is proposed. The design of address decoder, memory cell, and the layout are included. This approach adopts flip-flop array structure. The flip-...An approach to design small scale CMOS static random access memory (SRAM) is proposed. The design of address decoder, memory cell, and the layout are included. This approach adopts flip-flop array structure. The flip-flops are used as the storage cells and they are stacked to form the whole SRAM module. The word select bit is generated from the address decoder. And one word at a time is selected for reading or writing. The design of the memory core's layout is also discussed since it should be optimized to save area and also should be convenient for realization. It's a full-custom layout. The address decoder is composed of combinational logic circuit and its layout is also designed as a full-custom layout. With all these modules, the integral structure of the SRAM is carried out.展开更多
Functional failure mode of commercial deep sub-micron static random access memory（SRAM） induced by total dose irradiation is experimentally analyzed and verified by circuit simulation. We extensively characterize th...Functional failure mode of commercial deep sub-micron static random access memory（SRAM） induced by total dose irradiation is experimentally analyzed and verified by circuit simulation. We extensively characterize the functional failure mode of the device by testing its electrical parameters and function with test patterns covering different functional failure modes. Experimental results reveal that the functional failure mode of the device is a temporary function interruption caused by peripheral circuits being sensitive to the standby current rising. By including radiation-induced threshold shift and off-state leakage current in memory cell transistors, we simulate the influence of radiation on the functionality of the memory cell. Simulation results reveal that the memory cell is tolerant to irradiation due to its high stability, which agrees with our experimental result.展开更多
An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an intern...An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy（TMR）,which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.展开更多
A signal probability and activity probability (SPAP) model was proposed firstly, to estimate the impacts of the negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) on power ga...A signal probability and activity probability (SPAP) model was proposed firstly, to estimate the impacts of the negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) on power gated static random access memory (SRAM). The experiment results show that PBTI has significant influence on the read and write operations of SRAM with power gating, and it deteriorates the NBTI effects and results in a up to 39.38% static noise margin reduction and a 35.7% write margin degradation together with NBTI after 106 s working time. Then, a circuit level simulation was used to verify the assumption of the SPAP model, and finally the statistic data of CPU2000 benchmarks show that the proposed model has a reduction of 3.85% for estimation of the SNM degradation after 106 s working time compared with previous work.展开更多
Recent studies on carbon nanotube(CNT)field-effect transistors(FETs)and integrated circuits(ICs)have shown their potential in radiation tolerance.However,most studies have focused on the displacement damage(DD)effect ...Recent studies on carbon nanotube(CNT)field-effect transistors(FETs)and integrated circuits(ICs)have shown their potential in radiation tolerance.However,most studies have focused on the displacement damage(DD)effect and total ionizing dose(TID)effect,while the single event effect(SEE)remains insufficiently explored.In this work,we thoroughly examined the SEE of the CNT devices.Using a pulse laser as the irradiation source,the CNT FETs and static random-access memory(SRAM)exhibited an excellent radiation tolerance with a laser threshold energy of 5 nJ/pulse for SEE.Additionally,we used technology computer-aided design(TCAD)tools to explore SEE mechanisms of the CNT-based electronics.Owing to the nanoscale cross-sections and the special SEE mechanism of CNT,the CNT FETs and SRAMs present higher SEE tolerance compared to the Si-based devices,meaning that CNT based ICs can be an excellent technology for the applications of outer space exploration.展开更多
Monolithic three-dimensional(M3D)integration represents a transformative approach in semiconductor technology,enabling the vertical integration of diverse functionalities within a single chip.This review explores the ...Monolithic three-dimensional(M3D)integration represents a transformative approach in semiconductor technology,enabling the vertical integration of diverse functionalities within a single chip.This review explores the evolution of M3D integration from traditional bulk semiconductors to low-dimensional materials like two-dimensioanl(2D)transition metal dichalcogenides(TMDCs)and carbon nanotubes(CNTs).Key applications include logic circuits,static random access memory(SRAM),resistive random access memory(RRAM),sensors,optoelectronics,and artificial intelligence(AI)processing.M3D integration enhances device performance by reducing footprint,improving power efficiency,and alleviating the von Neumann bottleneck.The integration of 2D materials in M3D structures demonstrates significant advancements in terms of scalability,energy efficiency,and functional diversity.Challenges in manufacturing and scaling are discussed,along with prospects for future research directions.Overall,the M3D integration with low-dimensional materials presents a promising pathway for the development of next-generation electronic devices and systems.展开更多
SRAM-based computing-in-memory(SRAM-CIM)is expected to solve the“Memory Wall”problem.For the digital domain SRAM-CIM,full-precision digital logic has been utilized to achieve high computational accuracy.However,the ...SRAM-based computing-in-memory(SRAM-CIM)is expected to solve the“Memory Wall”problem.For the digital domain SRAM-CIM,full-precision digital logic has been utilized to achieve high computational accuracy.However,the energy and area efficiency advantages of CIM cannot be fully utilized under error-resilient neural networks(NNs)with given quantization bit-width.Therefore,an all-digital Bit-wise Approximate compressor configurable In-SRAM-computing macro for Energy-efficient NN acceleration,with a data-aware weight Remapping method(BASER),is proposed in this paper.Leveraging the NN error resilience property,six energy-efficient bit-wise compressor configurations are presented under 4b/4b and 3b/3b NN quantization,respectively.Concurrently,a data-aware weight remapping approach is proposed to enhance the NN accuracy without supplementary retraining further.Evaluations of VGG-9 and ResNet-18 on CIFAR-10 and CIFAR-100 datasets show that the proposed BASER achieves 1.35x and 1.29x improvement in energy efficiency,as well as limited accuracy loss and improved NN accuracy,as compared to the previous full-precision and approximate SRAM-CIM design,respectively.展开更多
基金the Beijing Natural Science Foundation under Grant No.JQ18013the National Natural Science Foundation of China under Grant Nos.61925208,61732007,61732002 and 61906179+1 种基金the Strategic Priority Research Program of Chinese Academy of Sciences(CAS)under Grant No.XDB32050200the Youth Innovation Promotion Association CAS,Beijing Academy of Artificial Intelligence(BAAI)and Xplore Prize.
文摘Uniform memory multicore neural network accelerators(UNNAs)furnish huge computing power to emerging neural network applications.Meanwhile,with neural network architectures going deeper and wider,the limited memory capacity has become a constraint to deploy models on UNNA platforms.Therefore how to efficiently manage memory space and how to reduce workload footprints are urgently significant.In this paper,we propose Tetris:a heuristic static memory management framework for UNNA platforms.Tetris reconstructs execution flows and synchronization relationships among cores to analyze each tensor’s liveness interval.Then the memory management problem is converted to a sequence permutation problem.Tetris uses a genetic algorithm to explore the permutation space to optimize the memory management strategy and reduce memory footprints.We evaluate several typical neural networks and the experimental results demonstrate that Tetris outperforms the state-of-the-art memory allocation methods,and achieves an average memory reduction ratio of 91.9%and 87.9%for a quad-core and a 16-core Cambricon-X platform,respectively.
基金supported by the State Key Program of the National Natural Science Foundation of China (Grant No.60836004)the National Natural Science Foundation of China (Grant Nos.61076025 and 61006070)
文摘Using computer-aided design three-dimensional （3D） simulation technology, the recovery mechanism of single event upset and the effects of spacing and hit angle on the recovery are studied. It is found that the multi-node charge collection plays a key role in recovery and shielding the charge sharing by adding guard rings. It cannot exhibit the recovery effect. It is also indicated that the upset linear energy transfer （LET） threshold is kept constant while the recovery LET threshold increases as the spacing increases. Additionally, the effect of incident angle on recovery is analysed and it is shown that a larger angle can bring about a stronger charge sharing effect, thus strengthening the recovery ability.
基金supported by the Open Foundation of State Key Laboratory of Electronic Thin Films and Integrated Devices,China(Grant No.KFJJ201306)
文摘Synergistic effects of the total ionizing dose （TID） on the single event upset （SEU） sensitivity in static random access memories （SRAMs） were studied by using protons. The total dose was cumulated with high flux protons during the TID exposure, and the SEU cross section was tested with low flux protons at several cumulated dose steps. Because of the radiation-induced off-state leakage current increase of the CMOS transistors, the noise margin became asymmetric and the memory imprint effect was observed.
基金supported by the National Key Laboratory of Materials Behavior and Evaluation Technology in Space Environment(No.6142910220208)National Natural Science Foundation of China(Nos.12105341 and 12035019)the opening fund of Key Laboratory of Silicon Device and Technology,Chinese Academy of Sciences(No.KLSDTJJ2022-3).
文摘This paper explores the impact of back-gate bias (V_(soi)) and supply voltage (V_(DD)) on the single-event upset (SEU) cross section of 0.18μm configurable silicon-on-insulator static random-access memory (SRAM) under high linear energy transfer heavyion experimentation.The experimental findings demonstrate that applying a negative back-gate bias to NMOS and a positive back-gate bias to PMOS enhances the SEU resistance of SRAM.Specifically,as the back-gate bias for N-type transistors(V_(nsoi)) decreases from 0 to-10 V,the SEU cross section decreases by 93.23%,whereas an increase in the back-gate bias for P-type transistors (V_(psoi)) from 0 to 10 V correlates with an 83.7%reduction in SEU cross section.Furthermore,a significant increase in the SEU cross section was observed with increase in supply voltage,as evidenced by a 159%surge at V_(DD)=1.98 V compared with the nominal voltage of 1.8 V.To explore the physical mechanisms underlying these experimental data,we analyzed the dependence of the critical charge of the circuit and the collected charge on the bias voltage by simulating SEUs using technology computer-aided design.
文摘In recent years,carbon nanotube field effect transistor(CNTFET)has become an attractive alternative to silicon for designing high-performance,highly stable,and low-power static random access memory(SRAM).SRAM serves as a cache memory in computers and many portable devices.Carbon nanotubes(CNTs),because of their exceptional transport capabilities,outstanding thermal conductivities,and impressive current handling capacities,have demonstrated great potential as an alternative device to the standard complementary metal-oxide-semiconductor(CMOS).The SRAM cell design using CNTFET is being compared to SRAM cell designs built using traditional CMOS technology.This paper presents the comprehensive analysis of CMOS&CNTFET based 8T SRAM cell design.Because of the nanoscale size,ballistic transport,and higher carrier mobility of the semiconducting nanotubes in CNTFET,it is integrated into the 8T SRAM cell.The approach incorporates several nonidealities,including the presence of quantum confinement consequences in the peripheral and transverse prescriptions,acoustic and transparent photon diffraction in the region surrounding the channel,as well as the screening effects by parallel CNTs in CNTFETs with multiple CNTs.By incorporating Stanford University CNTFET model in CADENCE(virtuoso)32 nm simulation,we have found that CNTFET SRAM cell is 4 times faster in terms of write/read delay and the write/read power delay product(PDP)value is almost 5 times lower compared to CMOS based SRAM.We have also analyzed the effect of temperature&different tube positions of CNTs on the performance evaluation of the 8T SRAM cell.
基金the National Key Research and Development Program of China(2018YFB2202602)The State Key Program of the National Natural Science Foundation of China(NO.61934005)+1 种基金The National Natural Science Foundation of China(NO.62074001)Joint Funds of the National Natural Science Foundation of China under Grant U19A2074.
文摘Artificial intelligence(AI)processes data-centric applications with minimal effort.However,it poses new challenges to system design in terms of computational speed and energy efficiency.The traditional von Neumann architecture cannot meet the requirements of heavily datacentric applications due to the separation of computation and storage.The emergence of computing inmemory(CIM)is significant in circumventing the von Neumann bottleneck.A commercialized memory architecture,static random-access memory(SRAM),is fast and robust,consumes less power,and is compatible with state-of-the-art technology.This study investigates the research progress of SRAM-based CIM technology in three levels:circuit,function,and application.It also outlines the problems,challenges,and prospects of SRAM-based CIM macros.
文摘Pattem imprinting in deep sub-micron static random access memories （SRAMs） during total dose irradiation is inves- tigated in detail. As the dose accumulates, the data pattern of memory cells loading during irradiation is gradually imprinted on their background data pattern. We build a relationship between the memory cell＇s static noise margin （SNM） and the background data, and study the influence of irradiation on the probability density function of ASNM, which is the difference between two data sides＇ SNMs, to discuss the reason for pattern imprinting. Finally, we demonstrate that, for micron and deep sub-micron devices, the mechanism of pattern imprinting is the bias-dependent threshold shift of the transistor, but for a deep sub-micron device the shift results from charge trapping in the shallow trench isolation （STI） oxide rather than from the gate oxide of the micron-device.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.U1532261 and 11605282)the Opening Fund of Key Laboratory of Silicon Device Technology,Chinese Academy of Sciences Research Projects(Grant No.KLSDTJJ2016-07)
文摘In this work, the total ionizing dose（TID） effect on 130 nm partially depleted（PD） silicon-on-insulator（SOI） static random access memory（SRAM） cell stability is measured. The SRAM cell test structure allowing direct measurement of the static noise margin（SNM） is specifically designed and irradiated by gamma-ray. Both data sides＇ SNM of 130 nm PD SOI SRAM cell are decreased by TID, which is different from the conclusion obtained in old generation devices that one data side＇s SNM is decreased and the other data side＇s SNM is increased. Moreover, measurement of SNM under different supply voltages（Vdd） reveals that SNM is more sensitive to TID under lower Vdd. The impact of TID on SNM under data retention Vddshould be tested, because Vddof SRAM cell under data retention mode is lower than normal Vdd.The mechanism under the above results is analyzed by measurement of I–V characteristics of SRAM cell transistors.
基金supported by the National Natural Science Foundation of China(Nos.12105341 and 12035019)the opening fund of Key Laboratory of Silicon Device and Technology,Chinese Academy of Sciences(No.KLSDTJJ2022-3).
文摘The 28 nm process has a high cost-performance ratio and has gradually become the standard for the field of radiation-hardened devices.However,owing to the minimum physical gate length of only 35 nm,the physical area of a standard 6T SRAM unit is approximately 0.16μm^(2),resulting in a significant enhancement of multi-cell charge-sharing effects.Multiple-cell upsets(MCUs)have become the primary physical mechanism behind single-event upsets(SEUs)in advanced nanometer node devices.The range of ionization track effects increases with higher ion energies,and spacecraft in orbit primarily experience SEUs caused by high-energy ions.However,ground accelerator experiments have mainly obtained low-energy ion irradiation data.Therefore,the impact of ion energy on the SEU cross section,charge collection mechanisms,and MCU patterns and quantities in advanced nanometer devices remains unclear.In this study,based on the experimental platform of the Heavy Ion Research Facility in Lanzhou,low-and high-energy heavy-ion beams were used to study the SEUs of 28 nm SRAM devices.The influence of ion energy on the charge collection processes of small-sensitive-volume devices,MCU patterns,and upset cross sections was obtained,and the applicable range of the inverse cosine law was clarified.The findings of this study are an important guide for the accurate evaluation of SEUs in advanced nanometer devices and for the development of radiation-hardening techniques.
基金the National Natural Science Foundation of China(Nos.12035019,11690041,and 11805244).
文摘A dual double interlocked storage cell(DICE)interleaving layout static random-access memory(SRAM)is designed and manufactured based on 65 nm bulk complementary metal oxide semiconductor technology.The single event upset(SEU)cross sections of this memory are obtained via heavy ion irradiation with a linear energy transfer(LET)value ranging from 1.7 to 83.4 MeV/(mg/cm^(2)).Experimental results show that the upset threshold(LETth)of a 4 KB block is approximately 6 MeV/(mg/cm^(2)),which is much better than that of a standard unhardened SRAM with an identical technology node.A 1 KB block has a higher LETth of 25 MeV/(mg/cm^(2))owing to the use of the error detection and correction(EDAC)code.For a Ta ion irradiation test with the highest LET value(83.4 MeV/(mg/cm^(2))),the benefit of the EDAC code is reduced significantly because the multi-bit upset proportion in the SEU is increased remarkably.Compared with normal incident ions,the memory exhibits a higher SEU sensitivity in the tilt angle irradiation test.Moreover,the SEU cross section indicates a significant dependence on the data pattern.When comprehensively considering HSPICE simulation results and the sensitive area distributions of the DICE cell,it is shown that the data pattern dependence is primarily associated with the arrangement of sensitive transistor pairs in the layout.Finally,some suggestions are provided to further improve the radiation resistance of the memory.By implementing a particular design at the layout level,the SEU tolerance of the memory is improved significantly at a low area cost.Therefore,the designed 65 nm SRAM is suitable for electronic systems operating in serious radiation environments.
基金supported by the National Natural Science Foundation of China (Grant Nos. 2032165 and 62004158)the National Key Scientific Instrument and Equipment Development Project of China (Grant No. 52127817)+1 种基金the State Key Laboratory of Particle Detection and Electronics (Grant Nos. SKLPDE-ZZ-201801 and SKLPDE-ZZ-202008)the Special Funds for Science and Technology Innovation Strategy of Guangdong Province, China (Grant No. 2018A0303130030)。
文摘To predict the soft error rate for applications, it is essential to study the energy dependence of the single-event-upset(SEU) cross-section. In this work, we present a direct measurement of the SEU cross-section with the Back-n white neutron source at the China Spallation Neutron Source. The measured cross section is consistent with the soft error data from the manufacturer and the result suggests that the threshold energy of the SEU is about 0.5 Me V, which confirms the statement in Iwashita’s report that the threshold energy for neutron soft error is much below that of the(n, α) cross-section of silicon.In addition, an index of the effective neutron energy is suggested to characterize the similarity between a spallation neutron beam and the standard atmospheric neutron environment.
文摘This paper develops a new simulation technique to characterize single event effects on semiconductor devices. The technique used to calculate the single event effects is developed according to the physical interaction mechanism of a single event effect. An application of the first principles simulation technique is performed to predict the ground-test single event upset effect on field-programmable gate arrays based on 0.25μm advanced complementary metal-oxidesemiconductor technology. The agreement between the single event upset cross section accessed from a broad-beam heavy ion experiment and simulation shows that the simulation technique could be used to characterize the single event effects induced by heavy ions on a semiconductor device.
基金Project supported by the National Natural Science Foundation of China(Grant No.U1532261)
文摘The pattern dependence in synergistic effects was studied in a 0.18 μm static random access memory（SRAM） circuit.Experiments were performed under two SEU test environments：3 Me V protons and heavy ions.Measured results show different trends.In heavy ion SEU test,the degradation in the peripheral circuitry also existed because the measured SEU cross section decreased regardless of the patterns written to the SRAM array.TCAD simulation was performed.TIDinduced degradation in n MOSFETs mainly induced the imprint effect in the SRAM cell,which is consistent with the measured results under the proton environment,but cannot explain the phenomena observed under heavy ion environment.A possible explanation could be the contribution from the radiation-induced GIDL in pMOSFETs.
文摘An approach to design small scale CMOS static random access memory (SRAM) is proposed. The design of address decoder, memory cell, and the layout are included. This approach adopts flip-flop array structure. The flip-flops are used as the storage cells and they are stacked to form the whole SRAM module. The word select bit is generated from the address decoder. And one word at a time is selected for reading or writing. The design of the memory core's layout is also discussed since it should be optimized to save area and also should be convenient for realization. It's a full-custom layout. The address decoder is composed of combinational logic circuit and its layout is also designed as a full-custom layout. With all these modules, the integral structure of the SRAM is carried out.
文摘Functional failure mode of commercial deep sub-micron static random access memory（SRAM） induced by total dose irradiation is experimentally analyzed and verified by circuit simulation. We extensively characterize the functional failure mode of the device by testing its electrical parameters and function with test patterns covering different functional failure modes. Experimental results reveal that the functional failure mode of the device is a temporary function interruption caused by peripheral circuits being sensitive to the standby current rising. By including radiation-induced threshold shift and off-state leakage current in memory cell transistors, we simulate the influence of radiation on the functionality of the memory cell. Simulation results reveal that the memory cell is tolerant to irradiation due to its high stability, which agrees with our experimental result.
基金Supported by the National High Technology and Development Program of China(2013AA1548)
文摘An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy（TMR）,which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.
基金Projects(60873016, 61170083) supported by the National Natural Science Foundation of ChinaProject(20114307110001) supported by the Doctoral Fund of Ministry of Education of China
文摘A signal probability and activity probability (SPAP) model was proposed firstly, to estimate the impacts of the negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) on power gated static random access memory (SRAM). The experiment results show that PBTI has significant influence on the read and write operations of SRAM with power gating, and it deteriorates the NBTI effects and results in a up to 39.38% static noise margin reduction and a 35.7% write margin degradation together with NBTI after 106 s working time. Then, a circuit level simulation was used to verify the assumption of the SPAP model, and finally the statistic data of CPU2000 benchmarks show that the proposed model has a reduction of 3.85% for estimation of the SNM degradation after 106 s working time compared with previous work.
基金supported by the National Natural Science Foundation of China(No.62301247)the Fundamental Research Funds for the Central Universities(No.2024300427)+2 种基金the Natural Science Foundation of Jiangsu Province(No.BK20230778)the Key Research and Development Program of Jiangsu Province(No.BK20232009)the Innovation Leading Talent Foundation of Suzhou(No.ZXL2023164).
文摘Recent studies on carbon nanotube(CNT)field-effect transistors(FETs)and integrated circuits(ICs)have shown their potential in radiation tolerance.However,most studies have focused on the displacement damage(DD)effect and total ionizing dose(TID)effect,while the single event effect(SEE)remains insufficiently explored.In this work,we thoroughly examined the SEE of the CNT devices.Using a pulse laser as the irradiation source,the CNT FETs and static random-access memory(SRAM)exhibited an excellent radiation tolerance with a laser threshold energy of 5 nJ/pulse for SEE.Additionally,we used technology computer-aided design(TCAD)tools to explore SEE mechanisms of the CNT-based electronics.Owing to the nanoscale cross-sections and the special SEE mechanism of CNT,the CNT FETs and SRAMs present higher SEE tolerance compared to the Si-based devices,meaning that CNT based ICs can be an excellent technology for the applications of outer space exploration.
基金fundings from the National Natural Science Foundation of China(Nos.62274013 and 92163206)the National Key Research and Development Program of China(No.2023YFB3405600)Science Fund for Creative Research Groups of the National Natural Science Foundation of China(No.12321004)。
文摘Monolithic three-dimensional(M3D)integration represents a transformative approach in semiconductor technology,enabling the vertical integration of diverse functionalities within a single chip.This review explores the evolution of M3D integration from traditional bulk semiconductors to low-dimensional materials like two-dimensioanl(2D)transition metal dichalcogenides(TMDCs)and carbon nanotubes(CNTs).Key applications include logic circuits,static random access memory(SRAM),resistive random access memory(RRAM),sensors,optoelectronics,and artificial intelligence(AI)processing.M3D integration enhances device performance by reducing footprint,improving power efficiency,and alleviating the von Neumann bottleneck.The integration of 2D materials in M3D structures demonstrates significant advancements in terms of scalability,energy efficiency,and functional diversity.Challenges in manufacturing and scaling are discussed,along with prospects for future research directions.Overall,the M3D integration with low-dimensional materials presents a promising pathway for the development of next-generation electronic devices and systems.
基金supported in part by the National Key R&D Program of China under Grant 2023YFB450220in part by the National Natural Science Foundation of China under Grant 62174110 and Grant 62104025in part by the Natural Science Foundation of Shanghai under Grant 23ZR1433200.
文摘SRAM-based computing-in-memory(SRAM-CIM)is expected to solve the“Memory Wall”problem.For the digital domain SRAM-CIM,full-precision digital logic has been utilized to achieve high computational accuracy.However,the energy and area efficiency advantages of CIM cannot be fully utilized under error-resilient neural networks(NNs)with given quantization bit-width.Therefore,an all-digital Bit-wise Approximate compressor configurable In-SRAM-computing macro for Energy-efficient NN acceleration,with a data-aware weight Remapping method(BASER),is proposed in this paper.Leveraging the NN error resilience property,six energy-efficient bit-wise compressor configurations are presented under 4b/4b and 3b/3b NN quantization,respectively.Concurrently,a data-aware weight remapping approach is proposed to enhance the NN accuracy without supplementary retraining further.Evaluations of VGG-9 and ResNet-18 on CIFAR-10 and CIFAR-100 datasets show that the proposed BASER achieves 1.35x and 1.29x improvement in energy efficiency,as well as limited accuracy loss and improved NN accuracy,as compared to the previous full-precision and approximate SRAM-CIM design,respectively.
