A 4H-SiC superjunction(SJ)MOSFET(SJMOS)with integrated high-K gate dielectric and split gate(HKSG-SJMOS)is proposed in this paper.The key features of HKSG-SJMOS involve the utilization of high-K(HK)dielectric as the g...A 4H-SiC superjunction(SJ)MOSFET(SJMOS)with integrated high-K gate dielectric and split gate(HKSG-SJMOS)is proposed in this paper.The key features of HKSG-SJMOS involve the utilization of high-K(HK)dielectric as the gate dielectric,which surrounds the source-connected split gate(SG)and metal gate.The high-K gate dielectric optimizes the electric field distribution within the drift region,creating a low-resistance conductive channel.This enhancement leads to an increase in the breakdown voltage(BV)and a reduction in the specific on resistance(R_(on,sp)).The introduction of split gate surrounded by high-K dielectric reduces the gate-drain capacitance(C_(gd))and gate-drain charge(Q_(gd)),which improves the switching characteristics.The simulation results indicate that compared to conventional 4H-SiC SJMOS,the HKSG-SJMOS exhibits a 110.5%enhancement in figure of merit(FOM,FOM=BV^(2)/R_(on,sp)),a 93.6%reduction in the high frequency figure of merit(HFFOM)of R_(on,sp)·C_(gd),and reductions in turn-on loss(E_(on))and turn-off loss(E_(off))by 38.3%and 31.6%,respectively.Furthermore,the reverse recovery characteristics of HKSG-SJMOS has also discussed,revealing superior performance compared to conventional 4H-SiC SJMOS.展开更多
Combining two-dimensional materials and high-k gate dielectrics offers a promising way to enhance the device performance of tunneling field-effect transistor(TFET).In this work,the device performance of WSe_(2)/SnSe_(...Combining two-dimensional materials and high-k gate dielectrics offers a promising way to enhance the device performance of tunneling field-effect transistor(TFET).In this work,the device performance of WSe_(2)/SnSe_(2)TFET with various gate dielectric materials is investigated based on quantum transport sim-ulation.Results show that TFETs with high-k gate dielectric materials exhibit improved on-offratio and enhanced transconductance.The optimized WSe_(2)/SnSe_(2)TFET with TiO_(2)gate dielectrics achieves an on-state current of 1560μA/μm and a subthreshold swing(SS)of 48 mV/dec.The utilization of high-k gate dielectric materials results in shorter tunneling length,higher transmission efficiency,and increased elec-tron tunneling probability.The performance of the WSe_(2)/SnSe_(2)TFET would be affected by the presence of the underlap region.Moreover,WSe_(2)/SnSe_(2)TFETs with La_(2)O_(3)dielectric can be scaled down to 3 nm while meeting high-performance(HP)device requirements according to the International Technology Roadmap for Semiconductors(ITRS).This research presents a practical solution for designing advanced logic devices in the sub-5 nm technology node.展开更多
The decreasing feature sizes in complementary metal-oxide semiconductor （CMOS） transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant （high-k） because...The decreasing feature sizes in complementary metal-oxide semiconductor （CMOS） transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant （high-k） because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability. In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology. Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties. It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling. In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices. Therefore, detailed atomic- scale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks, are highly required. In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed. Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy （HRTEM） and the related techniques based on scanning transmission electron microscopy （STEM）, including high-angle annular dark- field （HAADF） imaging （also known as Z-contrast imaging）, electron energy-loss spectroscopy （EELS）, and energy dispersive X-ray spectroscopy （EDS）, due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate stacks in the present and future generations of CMOS devices. In Section 1 of this review, the working principles of each technique are briefly introduced and their key features are outlined. In Section 2, microstructural characterizations of high-k gate dielectrics at atomic-scale by electron microscopy are critically reviewed by citing some recent results reported on high-k gate dielectrics. In Section 3, metal gate electrodes and the interfacial structures between high-k dielectrics and metal gates are discussed. The electron beam damage effects in high-k gate stacks are also evaluated, and their origins and prevention are described in Section 4. Finally, we end this review with personal perspectives towards the future challenges of atomic-scale material characterization in advanced CMOS gate stacks.展开更多
A physical model for mobility degradation by interface-roughness scattering and Coulomb scattering is proposed for SiGe p-MOSFET with a high-k dielectric/SiO2 gate stack. Impacts of the two kinds of scatterings on mob...A physical model for mobility degradation by interface-roughness scattering and Coulomb scattering is proposed for SiGe p-MOSFET with a high-k dielectric/SiO2 gate stack. Impacts of the two kinds of scatterings on mobility degradation are investigated. Effects of interlayer （SiO2） thickness and permittivities of the high-k dielectric and interlayer on carrier mobility are also discussed. It is shown that a smooth interface between high-k dielectric and interlayer, as well as moderate permittivities of high-k dielectrics, is highly desired to improve carriers mobility while keeping alow equivalent oxide thickness. Simulated results agree reasonably with experimental data.展开更多
Atomic layer deposited （ALD） Al2O3/dry-oxidized ultrathin SiO2 films as a high-k gate dielectric grown on 8° off-axis 4H-SiC （0001） epitaxial wafers are investigated in this paper. The metal-insulation-semico...Atomic layer deposited （ALD） Al2O3/dry-oxidized ultrathin SiO2 films as a high-k gate dielectric grown on 8° off-axis 4H-SiC （0001） epitaxial wafers are investigated in this paper. The metal-insulation-semiconductor （MIS） capacitors, respectively with different gate dielectric stacks （Al2O3/SiO2, Al2O3, and SiO2） are fabricated and compared with each other. The I-V measurements show that the Al2O3/SiO2 stack has a high breakdown field （≥12 MV/cm） comparable to SiO2, and a relatively low gate leakage current of 1 × 10-7 A/cm2 at an electric field of 4 MV/cm comparable to Al2O3. The 1-MHz high frequency C-V measurements exhibit that the Al2O3/SiO2 stack has a smaller positive flat-band voltage shift and hysteresis voltage, indicating a less effective charge and slow-trap density near the interface.展开更多
A new 2-Π lumped element equivalent circuit model for high-k stacked on-chip transformers is proposed. The model parameters are extracted with high precision, mainly based on analytical methods. The developed model e...A new 2-Π lumped element equivalent circuit model for high-k stacked on-chip transformers is proposed. The model parameters are extracted with high precision, mainly based on analytical methods. The developed model enables fast and accurate time domain transient analysis and noise analysis in RFIC simulation since all elements in the model are fre- quency independent. The validity of the proposed model has been demonstrated by a fabricated monolithic stacked trans- former in TSMC＇s 0.13μm mixed-signal （MS）/RF CMOS＇ process.展开更多
By complementing the equivalent oxide thickness （EOT） of a 1.7nm nitride/oxynitride （N/O） stack gate dielectric （EOT- 1.7nm） with a W/TiN metal gate electrode,metal gate CMOS devices with sub-100nm gate length a...By complementing the equivalent oxide thickness （EOT） of a 1.7nm nitride/oxynitride （N/O） stack gate dielectric （EOT- 1.7nm） with a W/TiN metal gate electrode,metal gate CMOS devices with sub-100nm gate length are fabricated in China for the first time. The key technologies adopted to restrain SCE and to improve drive ability include a 1.7nm N/O stack gate dielectric, non-CMP planarization technology, a T-type refractory W/TiN metal stack gate electrode, and a novel super steep retrograde channel doping using heavy ion implantation and a double sidewall scheme. Using these optimized key technologies, high performance 95nm metal gate CMOS devices with excellent SCE and good driving ability are fabricated. Under power supply voltages of VDS ± 1.5V and VGS± 1.8V,drive currents of 679μA/μm for nMOS and - 327μA/μm for pMOS are obtained. A subthreshold slope of 84.46mV/dec, DIBL of 34.76mV/V, and Vth of 0.26V for nMOS, and a subthreshold slope of 107.4mV/dec,DIBL of 54.46mV/V, and Vth of 0.27V for pMOS are achieved. These results show that the combined technology has indeed thoroughly eliminated the boron penetration phenomenon and polysilicon depletion effect ,effectively reduced gate tunneling leakage, and improved device reliability.展开更多
Dielectric elastomers(DEs)have emerged as one of the most promising artificial muscle technologies,due to their exceptional properties such as large actuation strain,fast response,high energy density,and flexible proc...Dielectric elastomers(DEs)have emerged as one of the most promising artificial muscle technologies,due to their exceptional properties such as large actuation strain,fast response,high energy density,and flexible processibility for various configurations.Over the past two decades,researchers have been working on developing DE materials with improved properties and exploring innovative applications of dielectric elastomer actuators(DEAs).This review article focuses on two main topics:recent material innovation of DEs and development of multilayer stacking processes for DEAs,which are important to promoting commercialization of DEs.It begins by explaining the working principle of a DEA.Then,recently developed strategies for preparing new DE materials are introduced,including reducing mechanical stiffness,increasing dielectric permittivity,suppressing viscoelasticity loss,and mitigating electromechanical instability without pre-stretching.In the next section,different multilayer stacking methods for fabricating multilayer DEAs are discussed,including conventional dry stacking,wet stacking,a novel dry stacking method,and micro-fabrication-enabled stacking techniques.This review provides a comprehensive and up-to-date overview of recent developments in high-performance DE materials and multilayer stacking methods.It highlights the progress made in the field and also discusses potential future directions for further advancements.展开更多
This paper presents a new silicon-on-insulator(SOI) lateral-double-diffused metal-oxide-semiconductor transistor(LDMOST) device with alternated high-k dielectric and step doped silicon pillars(HKSD device). Due to the...This paper presents a new silicon-on-insulator(SOI) lateral-double-diffused metal-oxide-semiconductor transistor(LDMOST) device with alternated high-k dielectric and step doped silicon pillars(HKSD device). Due to the modulation of step doping technology and high-k dielectric on the electric field and doped profile of each zone, the HKSD device shows a greater performance. The analytical models of the potential, electric field, optimal breakdown voltage, and optimal doped profile are derived. The analytical results and the simulated results are basically consistent, which confirms the proposed model suitable for the HKSD device. The potential and electric field modulation mechanism are investigated based on the simulation and analytical models. Furthermore, the influence of the parameters on the breakdown voltage(BV) and specific on-resistance(R_(on,sp)) are obtained. The results indicate that the HKSD device has a higher BV and lower R_(on,sp) compared to the SD device and HK device.展开更多
High-k gate dielectric Hf Ti ON Ga As metal-oxide–semiconductor（MOS） capacitors with La ON as interfacial passivation layer（IPL） and NH3- or N2-plasma surface pretreatment are fabricated, and their interfacial an...High-k gate dielectric Hf Ti ON Ga As metal-oxide–semiconductor（MOS） capacitors with La ON as interfacial passivation layer（IPL） and NH3- or N2-plasma surface pretreatment are fabricated, and their interfacial and electrical properties are investigated and compared with their counterparts that have neither La ON IPL nor surface treatment. It is found that good interface quality and excellent electrical properties can be achieved for a NH3-plasma pretreated Ga As MOS device with a stacked gate dielectric of Hf Ti ON/La ON. These improvements should be ascribed to the fact that the NH3-plasma can provide H atoms and NH radicals that can effectively remove defective Ga/As oxides. In addition, La ON IPL can further block oxygen atoms from being in-diffused, and Ga and As atoms from being out-diffused from the substrate to the high-k dielectric. This greatly suppresses the formation of Ga/As native oxides and gives rise to an excellent high-k/Ga As interface.展开更多
With the continued downscaling of complementary metal-oxide-semiconductor field effect transistor dimensions, high-dielectric constant （high-k） gate materials, as alternatives to SiO2, have been extensively investig...With the continued downscaling of complementary metal-oxide-semiconductor field effect transistor dimensions, high-dielectric constant （high-k） gate materials, as alternatives to SiO2, have been extensively investigated. Hf （Zr）-based high-k gate dielectric thin films have been regarded as the most promising candidates for high-k gate dielectric according to the International Technology Roadmap for Semiconductor due to their excellent physical properties and performance. This paper reviews the recent progress on Hf （Zr）-based high-k gate dielectrics based on PVD （physical vapor deposition） process. This article begins with a survey of various methods developed for generating Hf （Zr）-based high-k gate dielectrics, and then mainly focuses on microstructure, synthesis, characterization, formation mechanisms of interfacial layer, and optical properties of Hf （Zr）-based high-k gate dielectrics. Finally, this review concludes with personal perspectives towards future research on Hf （Zr）-based high-k gate dielectrics.展开更多
The fringing-induced barrier lowering（FIBL） effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain ...The fringing-induced barrier lowering（FIBL） effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect.The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance.Based on equivalent capacitance theory,the influences of channel length,junction depth,gate/lightly doped drain（LDD） overlap length,spacer material and spacer width on FIBL is thoroughly investigated.A stack gate dielectric is presented to suppress the FIBL effect.展开更多
NH3-plasma treatment is used to improve the quality of the gate dielectric and interface. Al2O3 is adopted as a buffer layer between HfO2 and MoS2 to decrease the interface-state density. Four groups of MOS capacitors...NH3-plasma treatment is used to improve the quality of the gate dielectric and interface. Al2O3 is adopted as a buffer layer between HfO2 and MoS2 to decrease the interface-state density. Four groups of MOS capacitors and back-gate transistors with different gate dielectrics are fabricated and their C–V and I–V characteristics are compared. It is found that the Al2O3/HfO2 back-gate transistor with NH3-plasma treatment shows the best electrical performance: high on–off current ratio of 1.53 × 107, higher field-effect mobility of 26.51 cm2/V·s, and lower subthreshold swing of 145 m V/dec.These are attributed to the improvements of the gate dielectric and interface qualities by the NH3-plasma treatment and the addition of Al2O3 as a buffer layer.展开更多
We investigate the influence of voltage drop across the lightly doped drain（LDD） region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overl...We investigate the influence of voltage drop across the lightly doped drain（LDD） region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson＇s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.展开更多
A multi-deposition multi-annealing technique （MDMA） is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device＇s performance. ...A multi-deposition multi-annealing technique （MDMA） is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device＇s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown （TDDB） characteristics of positive channel metal oxide semiconductor （PMOS） under different MDMA process conditions, including the depo- sition/annealing （D＆A） cycles, the D＆A time, and the total annealing time. The results show that the increases of the number of D＆A cycles （from 1 to 2） and D＆A time （from 15 s to 30 s） can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail （TTF） at 63.2% increases by about several times. However, too many D＆A cycles （such as 4 cycles） make the equivalent oxide thickness （EOT） increase by about 1A and the TTF of PMOS worsen. Moreover, different D＆A times and numbers of D＆A cycles induce different breakdown mechanisms.展开更多
High dielectric constant (high-k) materials are vital to the nanoelectronic devices. The paper reviews research development of high-k materials, describes a variety of manufacture technologies and discusses the applic...High dielectric constant (high-k) materials are vital to the nanoelectronic devices. The paper reviews research development of high-k materials, describes a variety of manufacture technologies and discusses the application of the gate stack systems to non-classical device structures.展开更多
This paper presents a method using simple physical vapour deposition to form high-quality hafnium silicon oxynitride （HfSiON） on ultrathin SiO2 buffer layer. The gate dielectric with 10A （1A = 0.1 nm） equivalent o...This paper presents a method using simple physical vapour deposition to form high-quality hafnium silicon oxynitride （HfSiON） on ultrathin SiO2 buffer layer. The gate dielectric with 10A （1A = 0.1 nm） equivalent oxide thickness is obtained. The experimental results indicate that the prepared HfSiON gate dielectric exhibits good physical and electrical characteristics, including very good thermal stability up to 1000℃, excellent interface properties, high dielectric constant （k = 14） and low gate-leakage current （Ig = 1.9 × 10^-3 A/cm^2@Vg = Vfb - 1 V for EOT of 10 A）. TaN metal gate electrode is integrated with the HfSiON gate dielectric.The effective work function of TaN on HfSiON is 4.3 eV, meeting the requirements of NMOS for the metal gate. And, the impacts of sputtering ambient and annealing temperature on the electrical properties of HfSiON gate dielectric are investigated.展开更多
Trichloroethylene （TCE） pretreatment of Si surface prior to HfO2 deposition is employed to fabricate HfO2 gatedielectric MOS capacitors. Influence of this processing procedure on interlayer growth, HfO2/Si interface...Trichloroethylene （TCE） pretreatment of Si surface prior to HfO2 deposition is employed to fabricate HfO2 gatedielectric MOS capacitors. Influence of this processing procedure on interlayer growth, HfO2/Si interface properties, gate-oxide leakage and device reliability is investigated. Among the surface pretreatments in NH3, NO, N2O and TCE ambients, the TCE pretreatment gives the least interlayer growths the lowest interface-state density, the smallest gate leakage and the highest reliability. All these improvements should be ascribed to the passivation effects of Cl2 and HC1 on the structural defects in the interlayer and at the interface, and also their gettering effects on the ion contamination in the gate dielectric.展开更多
Gd-doped HfO2 has drawn worldwide interest for its interesting features. It is considered to be a suitable material for N-type metal-oxide-semiconductor （MOS） devices due to a negative flatband voltage （Vfb） shift...Gd-doped HfO2 has drawn worldwide interest for its interesting features. It is considered to be a suitable material for N-type metal-oxide-semiconductor （MOS） devices due to a negative flatband voltage （Vfb） shift caused by the Gd doping. In this work, an anomalous positive shift was observed when Gd was doped into HfO2. The cause for such a phenomenon was systematically investigated by distinguishing the effects of different factors, such as Fermi level pinning （FLP）, a dipole at the dielectric/SiO2 interface, fixed interracial charge, and bulk charge, on Vfb. It was found that the FLP and interfacial dipole could make Vfb negatively shifted, which is in agreement with the conventional dipole theory. The increase in interfacial fixed charge resulting from Gd doping plays a major role in positive Vfb shift.展开更多
基金supported by the National Natural Science Foundation of China(Grant Nos.62074080 and U23B2042)in part by the Natural Science Foundation of Jiangsu Province(Grant No.BK20211104)in part by the Jiangsu Provincial Key Research and Development Program(Grant No.BE2022126)。
文摘A 4H-SiC superjunction(SJ)MOSFET(SJMOS)with integrated high-K gate dielectric and split gate(HKSG-SJMOS)is proposed in this paper.The key features of HKSG-SJMOS involve the utilization of high-K(HK)dielectric as the gate dielectric,which surrounds the source-connected split gate(SG)and metal gate.The high-K gate dielectric optimizes the electric field distribution within the drift region,creating a low-resistance conductive channel.This enhancement leads to an increase in the breakdown voltage(BV)and a reduction in the specific on resistance(R_(on,sp)).The introduction of split gate surrounded by high-K dielectric reduces the gate-drain capacitance(C_(gd))and gate-drain charge(Q_(gd)),which improves the switching characteristics.The simulation results indicate that compared to conventional 4H-SiC SJMOS,the HKSG-SJMOS exhibits a 110.5%enhancement in figure of merit(FOM,FOM=BV^(2)/R_(on,sp)),a 93.6%reduction in the high frequency figure of merit(HFFOM)of R_(on,sp)·C_(gd),and reductions in turn-on loss(E_(on))and turn-off loss(E_(off))by 38.3%and 31.6%,respectively.Furthermore,the reverse recovery characteristics of HKSG-SJMOS has also discussed,revealing superior performance compared to conventional 4H-SiC SJMOS.
基金supported by the National Natural Science Foun-dation of China(Grant Nos.62174122 and U2241244)the Fun-damental Research Funds for the Central Universities(Grant No.2042023kf0116)+1 种基金the Science and Technology Project of China Southern Power Grid Co.,Ltd.(Grant No.GXKJXM20220095)the Hubei Key Laboratory of Electronic Manufacturing and Pack-aging Integration of Wuhan University(Grant No.EMPI2023016)。
文摘Combining two-dimensional materials and high-k gate dielectrics offers a promising way to enhance the device performance of tunneling field-effect transistor(TFET).In this work,the device performance of WSe_(2)/SnSe_(2)TFET with various gate dielectric materials is investigated based on quantum transport sim-ulation.Results show that TFETs with high-k gate dielectric materials exhibit improved on-offratio and enhanced transconductance.The optimized WSe_(2)/SnSe_(2)TFET with TiO_(2)gate dielectrics achieves an on-state current of 1560μA/μm and a subthreshold swing(SS)of 48 mV/dec.The utilization of high-k gate dielectric materials results in shorter tunneling length,higher transmission efficiency,and increased elec-tron tunneling probability.The performance of the WSe_(2)/SnSe_(2)TFET would be affected by the presence of the underlap region.Moreover,WSe_(2)/SnSe_(2)TFETs with La_(2)O_(3)dielectric can be scaled down to 3 nm while meeting high-performance(HP)device requirements according to the International Technology Roadmap for Semiconductors(ITRS).This research presents a practical solution for designing advanced logic devices in the sub-5 nm technology node.
基金support from Natural Science Foundation of Jiangsu Province (ProjectNo. BK2007130)National Natural Science Foundation of China (Grant Nos. 10874065, 60576023 and 60636010)+3 种基金Ministry of Science and Technology of China (Grant No.2009CB929503)Ministry of Science and Technology of China (Grant Nos. 2009CB929503 and2009ZX02101-4)the project sponsored by the Scientific Research Foundation for the Returned Overseas Chinese Scholars, State Education MinistryNational Found for Fostering Talents of Basic Science (NFFTBS) (ProjectNo. J0630316)
文摘The decreasing feature sizes in complementary metal-oxide semiconductor （CMOS） transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant （high-k） because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability. In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology. Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties. It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling. In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices. Therefore, detailed atomic- scale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks, are highly required. In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed. Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy （HRTEM） and the related techniques based on scanning transmission electron microscopy （STEM）, including high-angle annular dark- field （HAADF） imaging （also known as Z-contrast imaging）, electron energy-loss spectroscopy （EELS）, and energy dispersive X-ray spectroscopy （EDS）, due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate stacks in the present and future generations of CMOS devices. In Section 1 of this review, the working principles of each technique are briefly introduced and their key features are outlined. In Section 2, microstructural characterizations of high-k gate dielectrics at atomic-scale by electron microscopy are critically reviewed by citing some recent results reported on high-k gate dielectrics. In Section 3, metal gate electrodes and the interfacial structures between high-k dielectrics and metal gates are discussed. The electron beam damage effects in high-k gate stacks are also evaluated, and their origins and prevention are described in Section 4. Finally, we end this review with personal perspectives towards the future challenges of atomic-scale material characterization in advanced CMOS gate stacks.
基金Project supported by the National Natural Science Foundation of China （Grant No 60776016）, the RGC of HKSAR, China （Grant No HKU7142/05E）, and Open Foundation of State Key Laboratory of Advanced Technology for Materials Synthesis and Processing （Grant No WUT2006M02）.
文摘A physical model for mobility degradation by interface-roughness scattering and Coulomb scattering is proposed for SiGe p-MOSFET with a high-k dielectric/SiO2 gate stack. Impacts of the two kinds of scatterings on mobility degradation are investigated. Effects of interlayer （SiO2） thickness and permittivities of the high-k dielectric and interlayer on carrier mobility are also discussed. It is shown that a smooth interface between high-k dielectric and interlayer, as well as moderate permittivities of high-k dielectrics, is highly desired to improve carriers mobility while keeping alow equivalent oxide thickness. Simulated results agree reasonably with experimental data.
基金Project supported by the National Natural Science Foundation of China （Grant Nos. 61006060 and 61176070）.
文摘Atomic layer deposited （ALD） Al2O3/dry-oxidized ultrathin SiO2 films as a high-k gate dielectric grown on 8° off-axis 4H-SiC （0001） epitaxial wafers are investigated in this paper. The metal-insulation-semiconductor （MIS） capacitors, respectively with different gate dielectric stacks （Al2O3/SiO2, Al2O3, and SiO2） are fabricated and compared with each other. The I-V measurements show that the Al2O3/SiO2 stack has a high breakdown field （≥12 MV/cm） comparable to SiO2, and a relatively low gate leakage current of 1 × 10-7 A/cm2 at an electric field of 4 MV/cm comparable to Al2O3. The 1-MHz high frequency C-V measurements exhibit that the Al2O3/SiO2 stack has a smaller positive flat-band voltage shift and hysteresis voltage, indicating a less effective charge and slow-trap density near the interface.
文摘A new 2-Π lumped element equivalent circuit model for high-k stacked on-chip transformers is proposed. The model parameters are extracted with high precision, mainly based on analytical methods. The developed model enables fast and accurate time domain transient analysis and noise analysis in RFIC simulation since all elements in the model are fre- quency independent. The validity of the proposed model has been demonstrated by a fabricated monolithic stacked trans- former in TSMC＇s 0.13μm mixed-signal （MS）/RF CMOS＇ process.
文摘By complementing the equivalent oxide thickness （EOT） of a 1.7nm nitride/oxynitride （N/O） stack gate dielectric （EOT- 1.7nm） with a W/TiN metal gate electrode,metal gate CMOS devices with sub-100nm gate length are fabricated in China for the first time. The key technologies adopted to restrain SCE and to improve drive ability include a 1.7nm N/O stack gate dielectric, non-CMP planarization technology, a T-type refractory W/TiN metal stack gate electrode, and a novel super steep retrograde channel doping using heavy ion implantation and a double sidewall scheme. Using these optimized key technologies, high performance 95nm metal gate CMOS devices with excellent SCE and good driving ability are fabricated. Under power supply voltages of VDS ± 1.5V and VGS± 1.8V,drive currents of 679μA/μm for nMOS and - 327μA/μm for pMOS are obtained. A subthreshold slope of 84.46mV/dec, DIBL of 34.76mV/V, and Vth of 0.26V for nMOS, and a subthreshold slope of 107.4mV/dec,DIBL of 54.46mV/V, and Vth of 0.27V for pMOS are achieved. These results show that the combined technology has indeed thoroughly eliminated the boron penetration phenomenon and polysilicon depletion effect ,effectively reduced gate tunneling leakage, and improved device reliability.
基金This work is supported by the National Natural Science Foundation of China(No.T229722).
文摘Dielectric elastomers(DEs)have emerged as one of the most promising artificial muscle technologies,due to their exceptional properties such as large actuation strain,fast response,high energy density,and flexible processibility for various configurations.Over the past two decades,researchers have been working on developing DE materials with improved properties and exploring innovative applications of dielectric elastomer actuators(DEAs).This review article focuses on two main topics:recent material innovation of DEs and development of multilayer stacking processes for DEAs,which are important to promoting commercialization of DEs.It begins by explaining the working principle of a DEA.Then,recently developed strategies for preparing new DE materials are introduced,including reducing mechanical stiffness,increasing dielectric permittivity,suppressing viscoelasticity loss,and mitigating electromechanical instability without pre-stretching.In the next section,different multilayer stacking methods for fabricating multilayer DEAs are discussed,including conventional dry stacking,wet stacking,a novel dry stacking method,and micro-fabrication-enabled stacking techniques.This review provides a comprehensive and up-to-date overview of recent developments in high-performance DE materials and multilayer stacking methods.It highlights the progress made in the field and also discusses potential future directions for further advancements.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61704084 and 61874059)。
文摘This paper presents a new silicon-on-insulator(SOI) lateral-double-diffused metal-oxide-semiconductor transistor(LDMOST) device with alternated high-k dielectric and step doped silicon pillars(HKSD device). Due to the modulation of step doping technology and high-k dielectric on the electric field and doped profile of each zone, the HKSD device shows a greater performance. The analytical models of the potential, electric field, optimal breakdown voltage, and optimal doped profile are derived. The analytical results and the simulated results are basically consistent, which confirms the proposed model suitable for the HKSD device. The potential and electric field modulation mechanism are investigated based on the simulation and analytical models. Furthermore, the influence of the parameters on the breakdown voltage(BV) and specific on-resistance(R_(on,sp)) are obtained. The results indicate that the HKSD device has a higher BV and lower R_(on,sp) compared to the SD device and HK device.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61176100 and 61274112)
文摘High-k gate dielectric Hf Ti ON Ga As metal-oxide–semiconductor（MOS） capacitors with La ON as interfacial passivation layer（IPL） and NH3- or N2-plasma surface pretreatment are fabricated, and their interfacial and electrical properties are investigated and compared with their counterparts that have neither La ON IPL nor surface treatment. It is found that good interface quality and excellent electrical properties can be achieved for a NH3-plasma pretreated Ga As MOS device with a stacked gate dielectric of Hf Ti ON/La ON. These improvements should be ascribed to the fact that the NH3-plasma can provide H atoms and NH radicals that can effectively remove defective Ga/As oxides. In addition, La ON IPL can further block oxygen atoms from being in-diffused, and Ga and As atoms from being out-diffused from the substrate to the high-k dielectric. This greatly suppresses the formation of Ga/As native oxides and gives rise to an excellent high-k/Ga As interface.
基金the support from the National Major Project of Fundamental Research:Nanomaterials and Nanostructures(Grant No.2005CB623603)the National Natural Science Foundation of China(Grant No.10674138)the Special Fund for President Scholarship,Chinese Academy of Sciences.
文摘With the continued downscaling of complementary metal-oxide-semiconductor field effect transistor dimensions, high-dielectric constant （high-k） gate materials, as alternatives to SiO2, have been extensively investigated. Hf （Zr）-based high-k gate dielectric thin films have been regarded as the most promising candidates for high-k gate dielectric according to the International Technology Roadmap for Semiconductor due to their excellent physical properties and performance. This paper reviews the recent progress on Hf （Zr）-based high-k gate dielectrics based on PVD （physical vapor deposition） process. This article begins with a survey of various methods developed for generating Hf （Zr）-based high-k gate dielectrics, and then mainly focuses on microstructure, synthesis, characterization, formation mechanisms of interfacial layer, and optical properties of Hf （Zr）-based high-k gate dielectrics. Finally, this review concludes with personal perspectives towards future research on Hf （Zr）-based high-k gate dielectrics.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.60936005 and 61076097)the Cultivation Fund of the Key Scientific and Technical Innovation Project of Ministry of Education of China(Grant No.708083)the Fundamental Research Funds for the Central Universities,China(Grant No.20110203110012)
文摘The fringing-induced barrier lowering（FIBL） effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect.The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance.Based on equivalent capacitance theory,the influences of channel length,junction depth,gate/lightly doped drain（LDD） overlap length,spacer material and spacer width on FIBL is thoroughly investigated.A stack gate dielectric is presented to suppress the FIBL effect.
基金Project supported by the National Natural Science Foundation of China(Grant No.61774064)
文摘NH3-plasma treatment is used to improve the quality of the gate dielectric and interface. Al2O3 is adopted as a buffer layer between HfO2 and MoS2 to decrease the interface-state density. Four groups of MOS capacitors and back-gate transistors with different gate dielectrics are fabricated and their C–V and I–V characteristics are compared. It is found that the Al2O3/HfO2 back-gate transistor with NH3-plasma treatment shows the best electrical performance: high on–off current ratio of 1.53 × 107, higher field-effect mobility of 26.51 cm2/V·s, and lower subthreshold swing of 145 m V/dec.These are attributed to the improvements of the gate dielectric and interface qualities by the NH3-plasma treatment and the addition of Al2O3 as a buffer layer.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.60936005 and 61076097)the Cultivation Fund of the Key Scientific and Technical Innovation Project,Ministry of Education of China(Grant No.708083)the Fundamental Research Funds for the Central Universities of China(Grant No.20110203110012)
文摘We investigate the influence of voltage drop across the lightly doped drain（LDD） region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson＇s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.
基金supported by the National High Technology Research and Development Program of China(Grant No.SS2015AA010601)the National Natural Science Foundation of China(Grant Nos.61176091 and 61306129)
文摘A multi-deposition multi-annealing technique （MDMA） is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device＇s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown （TDDB） characteristics of positive channel metal oxide semiconductor （PMOS） under different MDMA process conditions, including the depo- sition/annealing （D＆A） cycles, the D＆A time, and the total annealing time. The results show that the increases of the number of D＆A cycles （from 1 to 2） and D＆A time （from 15 s to 30 s） can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail （TTF） at 63.2% increases by about several times. However, too many D＆A cycles （such as 4 cycles） make the equivalent oxide thickness （EOT） increase by about 1A and the TTF of PMOS worsen. Moreover, different D＆A times and numbers of D＆A cycles induce different breakdown mechanisms.
文摘High dielectric constant (high-k) materials are vital to the nanoelectronic devices. The paper reviews research development of high-k materials, describes a variety of manufacture technologies and discusses the application of the gate stack systems to non-classical device structures.
基金supported by the State Key Development Program for Basic Research of China (Grant No 2006CB302704)the National Natural Science Foundation of China (Grant No 60776030)
文摘This paper presents a method using simple physical vapour deposition to form high-quality hafnium silicon oxynitride （HfSiON） on ultrathin SiO2 buffer layer. The gate dielectric with 10A （1A = 0.1 nm） equivalent oxide thickness is obtained. The experimental results indicate that the prepared HfSiON gate dielectric exhibits good physical and electrical characteristics, including very good thermal stability up to 1000℃, excellent interface properties, high dielectric constant （k = 14） and low gate-leakage current （Ig = 1.9 × 10^-3 A/cm^2@Vg = Vfb - 1 V for EOT of 10 A）. TaN metal gate electrode is integrated with the HfSiON gate dielectric.The effective work function of TaN on HfSiON is 4.3 eV, meeting the requirements of NMOS for the metal gate. And, the impacts of sputtering ambient and annealing temperature on the electrical properties of HfSiON gate dielectric are investigated.
基金Project supported by the National Natural Science Foundation of China （Grant No 60376019）.
文摘Trichloroethylene （TCE） pretreatment of Si surface prior to HfO2 deposition is employed to fabricate HfO2 gatedielectric MOS capacitors. Influence of this processing procedure on interlayer growth, HfO2/Si interface properties, gate-oxide leakage and device reliability is investigated. Among the surface pretreatments in NH3, NO, N2O and TCE ambients, the TCE pretreatment gives the least interlayer growths the lowest interface-state density, the smallest gate leakage and the highest reliability. All these improvements should be ascribed to the passivation effects of Cl2 and HC1 on the structural defects in the interlayer and at the interface, and also their gettering effects on the ion contamination in the gate dielectric.
基金Project supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China(Grant No.2009ZX02035)the National Natural Science of China(Grant Nos.61176091 and 50932001)
文摘Gd-doped HfO2 has drawn worldwide interest for its interesting features. It is considered to be a suitable material for N-type metal-oxide-semiconductor （MOS） devices due to a negative flatband voltage （Vfb） shift caused by the Gd doping. In this work, an anomalous positive shift was observed when Gd was doped into HfO2. The cause for such a phenomenon was systematically investigated by distinguishing the effects of different factors, such as Fermi level pinning （FLP）, a dipole at the dielectric/SiO2 interface, fixed interracial charge, and bulk charge, on Vfb. It was found that the FLP and interfacial dipole could make Vfb negatively shifted, which is in agreement with the conventional dipole theory. The increase in interfacial fixed charge resulting from Gd doping plays a major role in positive Vfb shift.
