The escalating need for high-performance artificial intelligence(AI)computing intensifies the"memory bottleneck"of the von Neumann architecture,prompting extensive exploration of computation-in-memory(CIM)so...The escalating need for high-performance artificial intelligence(AI)computing intensifies the"memory bottleneck"of the von Neumann architecture,prompting extensive exploration of computation-in-memory(CIM)solutions.This study is cen-tered on the optimization of a high-efficiency,low-power"L"-shaped split-gate floating-gate(FG)memory for CIM applications.Fabricated on a 55 nm CMOS platform,the memory devices were systematically investigated through wafer acceptance test(WAT),Sentaurus^(TM)simulations and comprehensive evaluations with the DNN+NeuroSim Framework V2.0.Among devices with diverse FG lengths,the 95-nm FG variant exhibits outstanding performance:it achieves a 5.35 V memory window,reaches a maximum conductance of 16.7μS with excellent linearity under the varying voltage and width pulse scheme(VWPS),real-izes 32-state multi-level storage,and attains a 92%training accuracy on the CIFAR-10 dataset using the VGG8 neural network.展开更多
Data retention is one of the most important reliability characteristics of split-gate flash.Therefore,many efforts were made to improve data retention of split-gate flash.By experiments,it was found that higher chlori...Data retention is one of the most important reliability characteristics of split-gate flash.Therefore,many efforts were made to improve data retention of split-gate flash.By experiments,it was found that higher chlorine concentration produced in FGSP2 oxide deposition can induce worse data retention.Thus,reducing chlorine concentration is an effective approach to improve data retention for split-gate flash product.Additional RTO annealing between FGSP2 oxide deposition and FGSP2 etching could reduce chlorine concentration,and improve FGSP2 oxide film quality,and then get better data retention.展开更多
A fully self-aligned symmetrical split-gate cell structure for 2-bit per cell flash memory with a very competitive bit size is presented. One common select gate is located between two floating gates and a pair of sour...A fully self-aligned symmetrical split-gate cell structure for 2-bit per cell flash memory with a very competitive bit size is presented. One common select gate is located between two floating gates and a pair of source/drain junctions are shared by the 2 bits. The fabrication method utilized here to create a self-aligned structure is to form a spacer against the prior layer without any additional mask. Although the cell consists of three channels in a series, the attributes from conventional split gate flash are still preserved with appropriate bias conditions. Program and erase operation is performed by using a source side injection （SSI） and a poly-to-poly tunneling mechanism respectively.展开更多
The erase voltage impact on the 0.18μm triple self-aligned split-gate flash endurance is studied.An optimized erase voltage is necessary in order to achieve the best endurance.A lower erase voltage can cause more cel...The erase voltage impact on the 0.18μm triple self-aligned split-gate flash endurance is studied.An optimized erase voltage is necessary in order to achieve the best endurance.A lower erase voltage can cause more cell current degradation by increasing its sensitivity to the floating gate voltage drop,which is induced by tunnel oxide charge trapping during program/erase cycling.A higher erase voltage also aggravates the endurance degradation by introducing select gate oxide charge trapping.A progressive erase voltage method is proposed and demonstrated to better balance the two degradation mechanisms and thus further improve endurance performance.展开更多
基金supported by National Key Research and Development Program of China (2022YFF0605803)Zhejiang key R&D project (2023C01017)+1 种基金the Zhejiang Key Research and Development Project (2024SJCZX0030)Zhejiang Technology Innovation Center of CMOS IC Manufacture Process and Design for supporting us to do this research.
文摘The escalating need for high-performance artificial intelligence(AI)computing intensifies the"memory bottleneck"of the von Neumann architecture,prompting extensive exploration of computation-in-memory(CIM)solutions.This study is cen-tered on the optimization of a high-efficiency,low-power"L"-shaped split-gate floating-gate(FG)memory for CIM applications.Fabricated on a 55 nm CMOS platform,the memory devices were systematically investigated through wafer acceptance test(WAT),Sentaurus^(TM)simulations and comprehensive evaluations with the DNN+NeuroSim Framework V2.0.Among devices with diverse FG lengths,the 95-nm FG variant exhibits outstanding performance:it achieves a 5.35 V memory window,reaches a maximum conductance of 16.7μS with excellent linearity under the varying voltage and width pulse scheme(VWPS),real-izes 32-state multi-level storage,and attains a 92%training accuracy on the CIFAR-10 dataset using the VGG8 neural network.
文摘Data retention is one of the most important reliability characteristics of split-gate flash.Therefore,many efforts were made to improve data retention of split-gate flash.By experiments,it was found that higher chlorine concentration produced in FGSP2 oxide deposition can induce worse data retention.Thus,reducing chlorine concentration is an effective approach to improve data retention for split-gate flash product.Additional RTO annealing between FGSP2 oxide deposition and FGSP2 etching could reduce chlorine concentration,and improve FGSP2 oxide film quality,and then get better data retention.
文摘A fully self-aligned symmetrical split-gate cell structure for 2-bit per cell flash memory with a very competitive bit size is presented. One common select gate is located between two floating gates and a pair of source/drain junctions are shared by the 2 bits. The fabrication method utilized here to create a self-aligned structure is to form a spacer against the prior layer without any additional mask. Although the cell consists of three channels in a series, the attributes from conventional split gate flash are still preserved with appropriate bias conditions. Program and erase operation is performed by using a source side injection （SSI） and a poly-to-poly tunneling mechanism respectively.
文摘The erase voltage impact on the 0.18μm triple self-aligned split-gate flash endurance is studied.An optimized erase voltage is necessary in order to achieve the best endurance.A lower erase voltage can cause more cell current degradation by increasing its sensitivity to the floating gate voltage drop,which is induced by tunnel oxide charge trapping during program/erase cycling.A higher erase voltage also aggravates the endurance degradation by introducing select gate oxide charge trapping.A progressive erase voltage method is proposed and demonstrated to better balance the two degradation mechanisms and thus further improve endurance performance.
