Data retention is one of the most important reliability characteristics of split-gate flash.Therefore,many efforts were made to improve data retention of split-gate flash.By experiments,it was found that higher chlori...Data retention is one of the most important reliability characteristics of split-gate flash.Therefore,many efforts were made to improve data retention of split-gate flash.By experiments,it was found that higher chlorine concentration produced in FGSP2 oxide deposition can induce worse data retention.Thus,reducing chlorine concentration is an effective approach to improve data retention for split-gate flash product.Additional RTO annealing between FGSP2 oxide deposition and FGSP2 etching could reduce chlorine concentration,and improve FGSP2 oxide film quality,and then get better data retention.展开更多
A fully self-aligned symmetrical split-gate cell structure for 2-bit per cell flash memory with a very competitive bit size is presented. One common select gate is located between two floating gates and a pair of sour...A fully self-aligned symmetrical split-gate cell structure for 2-bit per cell flash memory with a very competitive bit size is presented. One common select gate is located between two floating gates and a pair of source/drain junctions are shared by the 2 bits. The fabrication method utilized here to create a self-aligned structure is to form a spacer against the prior layer without any additional mask. Although the cell consists of three channels in a series, the attributes from conventional split gate flash are still preserved with appropriate bias conditions. Program and erase operation is performed by using a source side injection （SSI） and a poly-to-poly tunneling mechanism respectively.展开更多
The erase voltage impact on the 0.18μm triple self-aligned split-gate flash endurance is studied.An optimized erase voltage is necessary in order to achieve the best endurance.A lower erase voltage can cause more cel...The erase voltage impact on the 0.18μm triple self-aligned split-gate flash endurance is studied.An optimized erase voltage is necessary in order to achieve the best endurance.A lower erase voltage can cause more cell current degradation by increasing its sensitivity to the floating gate voltage drop,which is induced by tunnel oxide charge trapping during program/erase cycling.A higher erase voltage also aggravates the endurance degradation by introducing select gate oxide charge trapping.A progressive erase voltage method is proposed and demonstrated to better balance the two degradation mechanisms and thus further improve endurance performance.展开更多
文摘Data retention is one of the most important reliability characteristics of split-gate flash.Therefore,many efforts were made to improve data retention of split-gate flash.By experiments,it was found that higher chlorine concentration produced in FGSP2 oxide deposition can induce worse data retention.Thus,reducing chlorine concentration is an effective approach to improve data retention for split-gate flash product.Additional RTO annealing between FGSP2 oxide deposition and FGSP2 etching could reduce chlorine concentration,and improve FGSP2 oxide film quality,and then get better data retention.
文摘A fully self-aligned symmetrical split-gate cell structure for 2-bit per cell flash memory with a very competitive bit size is presented. One common select gate is located between two floating gates and a pair of source/drain junctions are shared by the 2 bits. The fabrication method utilized here to create a self-aligned structure is to form a spacer against the prior layer without any additional mask. Although the cell consists of three channels in a series, the attributes from conventional split gate flash are still preserved with appropriate bias conditions. Program and erase operation is performed by using a source side injection （SSI） and a poly-to-poly tunneling mechanism respectively.
文摘The erase voltage impact on the 0.18μm triple self-aligned split-gate flash endurance is studied.An optimized erase voltage is necessary in order to achieve the best endurance.A lower erase voltage can cause more cell current degradation by increasing its sensitivity to the floating gate voltage drop,which is induced by tunnel oxide charge trapping during program/erase cycling.A higher erase voltage also aggravates the endurance degradation by introducing select gate oxide charge trapping.A progressive erase voltage method is proposed and demonstrated to better balance the two degradation mechanisms and thus further improve endurance performance.
