We report an effective method to improve the performance of p-type copper phthalocyanine （CuPc） based organic field-effect transistors （OFETs） by employing a thin para-quaterphenyl （p-4p） film and simultane- ous...We report an effective method to improve the performance of p-type copper phthalocyanine （CuPc） based organic field-effect transistors （OFETs） by employing a thin para-quaterphenyl （p-4p） film and simultane- ously applying V205 to the source/drain regions. The p-4p layer was inserted between the insulating layer and the active layer, and V205 layer was added between CuPc and A1 in the source-drain （S/D） area. As a result, the field- effect saturation mobility and on/off current ratio of the optimized device were improved to 5 × 10-2 cm2/（V.s） and 104, respectively. We believe that because p-4p could induce CuPc to form a highly oriented and continuous film, this resulted in the better injection and transport of the carriers. Moreover, by introducing the V205 electrode＇s modified layers, the height of the carrier injection barrier could be effectively tuned and the contact resistance could be reduced.展开更多
In vertical channel transistors(VCTs),source/drain ion implantation(I/I)represents a significant technical challenge due to inherent three-dimensional structural constraints,which induce complications such as difficul...In vertical channel transistors(VCTs),source/drain ion implantation(I/I)represents a significant technical challenge due to inherent three-dimensional structural constraints,which induce complications such as difficulties in dummy gate forma-tion and shadowing effects of I/I.This article systematically investigates the impact of different implantation conditions on the performance of VCTs with and without dummy gates through TCAD simulation.It reveals the significant role of the lightly doped regions(LDRs)naturally formed due to ion implantation in source/drain of VCTs.Furthermore,it was found that VCT with-out dummy gates can achieve an approximately 27%increase in on-state current(Ion)under the same implantation conditions,and can greatly simplify the process flow and reduce costs.Finally,N-type and P-type VCTs were successfully fabricated using this implantation method.展开更多
m thin-film fully-depleted SOI CMOS devices with elevated source/drain structure are fabricated by a novel technology.Key process technologies are demonstrated.The devices have quasi-ideal subthreshold properties;the ...m thin-film fully-depleted SOI CMOS devices with elevated source/drain structure are fabricated by a novel technology.Key process technologies are demonstrated.The devices have quasi-ideal subthreshold properties;the subthreshold slope of nMOSFETs is 65mV/decade,while that of pMOSFETs is 69mV/decade.The saturation current of 1.2μm nMOSFETs is increased by 32% with elevated source/drain structure,and that of 1.2μm pMOSFETs is increased by 24%.The per-stage propagation delay of 101-stage fully-depleted SOI CMOS ring oscillator is 75ps with 3V supply voltage.展开更多
The effects of source-drain underlaps on the performance of a top gate silicon nanowire on insulator transistor are studied using a three dimensional(3D) self-consistent Poisson-Schrodinger quantum simulation. Voltage...The effects of source-drain underlaps on the performance of a top gate silicon nanowire on insulator transistor are studied using a three dimensional(3D) self-consistent Poisson-Schrodinger quantum simulation. Voltage-controlled tunnel barrier is the device transport physics. The off current, the on/off current ratio, and the inverse subthreshold slope are improved while the on current is degraded with underlap. The physics behind this behavior is the modulation of a tunnel barrier with underlap. The underlap primarily affects the tunneling component of drain current. About 50% contribution to the gate capacitance comes from the fringing electric fields emanating from the gate metal to the source and drain. The gate capacitance reduces with underlap, which should reduce the intrinsic switching delay and increase the intrinsic cut-off frequency. However, both the on current and the transconductance reduce with underlap, and the consequence is the increase of delay and the reduction of cut-off frequency.展开更多
Ge complementary tunneling field-effect transistors（TFETs） are fabricated with the NiGe metal source/drain（S/D） structure. The dopant segregation method is employed to form the NiGe/Ge tunneling junctions of suffi...Ge complementary tunneling field-effect transistors（TFETs） are fabricated with the NiGe metal source/drain（S/D） structure. The dopant segregation method is employed to form the NiGe/Ge tunneling junctions of sufficiently high Schottky barrier heights. As a result, the Ge p-and n-TFETs exhibit decent electrical properties of large ON-state current and steep sub-threshold slope（S factor）. Especially, I_d of 0.2 μA/μm is revealed at V_g-V_（th） = V_d = ±0.5 V for Ge pTFETs,with the S factor of 28 mV/dec at 7 K.展开更多
Fin field-effect transistor(FinFET)technology has been introduced to the mainstream complementary metal-oxide semiconductor(CMOS)manufacturing for low-power and highperformance applications.However,advanced FinFET nod...Fin field-effect transistor(FinFET)technology has been introduced to the mainstream complementary metal-oxide semiconductor(CMOS)manufacturing for low-power and highperformance applications.However,advanced FinFET nodes are facing significant challenges to enhance the device performance due to the increasingly prominent parasitic resistance and capacitance.In this study,for the first time,we demonstrate methods of enhancing p-channel FinFET(pFET)performance on a fully integrated advanced FinFET platform via source/drain(S/D)cavity structure optimization.By modulating the cavity depth and proximity around the optimal reference point,we show that the trade-off between the S/D resistance and short channel effect,as well as the impact on the parasitic capacitance must be considered for the S/D cavity structure optimization.An extra process knob of applying cavity implant on the desired cavity structure was also demonstrated to modify the S/D junction profile for device performance enhancement.展开更多
Effect of heat source sliding contact on the CoPtCr-based magnetic recording disk was investigated.A tribo-test of the disk with low load heat source and the scan of disk with magnetic head were sequentially carried o...Effect of heat source sliding contact on the CoPtCr-based magnetic recording disk was investigated.A tribo-test of the disk with low load heat source and the scan of disk with magnetic head were sequentially carried out.Then disk samples in the contact area were observed by atomic force microscopy(AFM)and magnetic force microscopy(MFM).A finite element model using thermomechanical coupling was developed to calculate the mechanical and thermal response of the disk under heat source sliding contact based on the experimental results.It was found that data loss load under sliding contact with a heat source was far less than that without a heat source,and mechanical scratches and demagnetization did not occur in the data loss area under the experimental conditions.The finite element analysis(FEA)results indicate that the thin surface DLC coating has more significant effect on the mechanical response than the thermal response of the magnetic layer.展开更多
Source-contacting gas, which is also called basin-center gas, deep basin gas, is the tight-sand gas accumulation contacting closely to its source rocks. Having different accumulation mechanisms from conventional gas r...Source-contacting gas, which is also called basin-center gas, deep basin gas, is the tight-sand gas accumulation contacting closely to its source rocks. Having different accumulation mechanisms from conventional gas reservoirs that are formed by replacement way, the typical source-contacting gas reservoirs are formed by piston-typed migration forward way. Source-contacting gas accumulations exhibit a series of distinctly mechanic characteristics. According to the valid combination of these characteristics, the estimation for the type of discovered gas reservoirs or distributions of source-contacting gas reservoirs can be forecasted. The source-contacting gas is special for having no edge water or bottom water for gas and complicated gas-water relationships, which emphasizes the intimate association of reservoir rocks with source rocks, which is called the root of the gas reservoir. There are many basins having the mechanic conditions for source-contacting gas accumulations in China, which can be divided into three regions. Most of the basins with favorable accumulation conditions are located mainly in the central and western China. According to the present data, basins having source-contacting gas accumulations in China can be divided into three types, accumulation conditions and configuration relationships are the best in type A basins and they are the larger basins in central China. Type B basins with plain accumulation conditions exist primarily in eastern China and also the basins in western China. Accumulation conditions and exploration futures are worse in type C basins, which refer mainly to the small basins in southern China and China Sea basins. Main source-contacting gas basins in China are thoroughly discussed in this paper and the distribution patterns of source-contacting gas in five huge basins are discussed and forecasted.展开更多
In this paper, we propose a novel Schottky barrier MOSFET structure, in which the silicide source/drain is designed on the buried metal （SSDOM）. The source/drain region consists of two layers of silicide materials. ...In this paper, we propose a novel Schottky barrier MOSFET structure, in which the silicide source/drain is designed on the buried metal （SSDOM）. The source/drain region consists of two layers of silicide materials. Two Schottky barriers are formed between the silicide layers and the silicon channel. In the device design, the top barrier is lower and the bottom is higher. The lower top contact barrier is to provide higher on-state current, and the higher bottom contact barrier to reduce the off-state current. To achieve this, ErSi is proposed for the top silicide and CoSi2 for the bottom in the n-channel ease. The 50 nm n-channel SSDOM is thus simulated to analyse the performance of the SSDOM device. In the simulations, the top contact barrier is 0.2e V （for ErSi） and the bottom barrier is 0.6 eV （for CoSi2）. Compared with the corresponding conventional Schottky barrier MOSFET structures （CSB）, the high on-state current of the SSDOM is maintained, and the off-state current is efficiently reduced. Thus, the high drive ability （1.2 mA/μm at Vds = 1 V, Vgs = 2 V） and the high Ion/Imin ratio （10^6） are both achieved by applying the SSDOM structure.展开更多
A new modified Angelov current–voltage characteristic model equation is proposed to improve the drain–source current（Ids） simulation of an Al Ga N/Ga N-based（gallium nitride） high electron mobility transistor（A...A new modified Angelov current–voltage characteristic model equation is proposed to improve the drain–source current（Ids） simulation of an Al Ga N/Ga N-based（gallium nitride） high electron mobility transistor（Al Ga N/Ga N-based HEMT） at high power operation. Since an accurate radio frequency（RF） current simulation is critical for a correct power simulation of the device, in this paper we propose a method of Al Ga N/Ga N high electron mobility transistor（HEMT）nonlinear large-signal model extraction with a supplemental modeling of RF drain–source current as a function of RF input power. The improved results of simulated output power, gain, and power added efficiency（PAE） at class-AB quiescent bias of Vgs =-3.5 V, Vds= 30 V with a frequency of 9.6 GHz are presented.展开更多
We investigate the influence of source and drain bias voltages(V_(DS))on the quantum sub-band transport spectrum in the 10-nm width N-typed junctionless nanowire transistor at the low temperature of 6 K.We demonstrate...We investigate the influence of source and drain bias voltages(V_(DS))on the quantum sub-band transport spectrum in the 10-nm width N-typed junctionless nanowire transistor at the low temperature of 6 K.We demonstrate that the transverse electric field introduced from V_(DS) has a minor influence on the threshold voltage of the device.The transverse electric field plays the role of amplifying the gate restriction effect of the channel.The one-dimensional(1D)-band dominated transport is demonstrated to be modulated by V_(DS) in the saturation region and the linear region,with the sub-band energy levels in the channel(E_(channel))intersecting with Fermi levels of the source(E_(fS))and the drain(E_(fD))in turn as V_(g) increases.The turning points from the linear region to the saturation region shift to higher gate voltages with V_(DS) increase because the higher Fermi energy levels of the channel required to meet the situation of E_(fD)=E_(channel).We also find that the bias electric field has the effect to accelerate the thermally activated electrons in the channel,equivalent to the effect of thermal temperature on the increase of electron energy.Our work provides a detailed description of the bias-modulated quantum electronic properties,which will give a more comprehensive understanding of transport behavior in nanoscale devices.展开更多
In this paper, a surface potential based threshold voltage model of fully-depleted（FD） recessed-source/drain（Re-S/D）silicon-on-insulator（SOI） metal-oxide semiconductor field-effect transistor（MOSFET） is presen...In this paper, a surface potential based threshold voltage model of fully-depleted（FD） recessed-source/drain（Re-S/D）silicon-on-insulator（SOI） metal-oxide semiconductor field-effect transistor（MOSFET） is presented while considering the effects of high-k gate-dielectric material induced fringing-field. The two-dimensional（2D） Poisson＇s equation is solved in a channel region in order to obtain the surface potential under the assumption of the parabolic potential profile in the transverse direction of the channel with appropriate boundary conditions. The accuracy of the model is verified by comparing the model＇s results with the 2D simulation results from ATLAS over a wide range of channel lengths and other parameters,including the dielectric constant of gate-dielectric material.展开更多
Rectangular Schottky drain AlGaN/AlN/GaN heterostructure field-effect transistors （HFETs） with different gate contact areas and conventional AlGaN/AlN/GaN HFETs as control were both fabricated with same size. It was...Rectangular Schottky drain AlGaN/AlN/GaN heterostructure field-effect transistors （HFETs） with different gate contact areas and conventional AlGaN/AlN/GaN HFETs as control were both fabricated with same size. It was found there is a significant difference between Schottky drain AlGaN/AlN/GaN HFETs and the control group both in drain series resistance and in two-dimensional electron gas （2DEG） electron mobility in the gate–drain channel. We attribute this to the different influence of Ohmic drain contacts and Schottky drain contacts on the strained AlGaN barrier layer. For conventional AlGaN/AlN/GaN HFETs, annealing drain Ohmic contacts gives rise to a strain variation in the AlGaN barrier layer between the gate contacts and the drain contacts, and results in strong polarization Coulomb field scattering in this region. In Schottky drain AlGaN/AlN/GaN HFETs, the strain in the AlGaN barrier layer is distributed more regularly.展开更多
Two-dimensional DC and small-signal analysis of gate-to-source scaling effects in SiC-based high-power field-effect transistors have been performed in this paper. The simulation results show that a downscaling of gate...Two-dimensional DC and small-signal analysis of gate-to-source scaling effects in SiC-based high-power field-effect transistors have been performed in this paper. The simulation results show that a downscaling of gate-to-source distance can improve device performance, i.e. enhancing drain current, transconductance, and maximum oscillation frequency. This is associated with the peculiar dynamic of electrons in SiC MESFETs, which lead to a linear velocity regime in the source access region. The variations of gate-to-source capacitance, gate-to-drain capacitance, and cut-off frequency with respect to the change in gate-to-source length have also been studied in detail.展开更多
为解决碳化硅金属氧化物半导体场效应晶体管(SiC Metal Oxide Semiconductor Field Effect Transistor,SiC MOSFET)硬开关故障(Hard Switch Fault,HSF)、负载故障(Fault Under Load,FUL)和过载故障(OverLoad fault,OL)的问题,本文提出...为解决碳化硅金属氧化物半导体场效应晶体管(SiC Metal Oxide Semiconductor Field Effect Transistor,SiC MOSFET)硬开关故障(Hard Switch Fault,HSF)、负载故障(Fault Under Load,FUL)和过载故障(OverLoad fault,OL)的问题,本文提出了一种基于SiC MOSFET漏极电压和源极电压检测的过流保护方法(OverCurrent Protection method based on the Drain-voltage and Source-voltage Detection,DSD-OCP).该方法通过检测电路实时监控SiC MOSFET的漏极电压和源极电压来准确识别短路故障和过载故障,并利用驱动电路控制SiC MOSFET的开通和关断,从而实现快速短路保护和自适应过载保护,同时还集成软关断功能.基于0.5μm双极型-互补金属氧化物半导体-双扩散金属氧化物半导体(Bipolar-CMOS-DMOS,BCD)工艺,设计了DSD-OCP电路并进行流片,芯片面积为2.8 mm^(2).采用研制的芯片搭建1200 V/80 mΩSiC MOSFET测试平台,并验证了DSD-OCP方法的有效性.实验结果表明,SiC MOSFET在DSD-OCP芯片保护下的HSF和FUL持续时间分别为88 ns和105 ns.在不同母线电压下,DSD-OCP芯片能够为SiC MOSFET提供自适应的过载保护.因DSD-OCP芯片具有软关断功能,SiC MOSFET在过流保护时的漏极电压过冲不超过110 V.展开更多
基金Project supported by the National Natural Science Foundation of China(No.60676051)the National High Technology Research and Development Program of China(No.2013A A014201)+2 种基金the Scientific Developing Foundation of Tianjin Education Commission(No.2011ZD02)the Key Science and Technology Support Program of Tianjin(No.14ZCZDGX00006)the Foundation of Key Discipline of Material Physics and Chemistry of Tianjin
文摘We report an effective method to improve the performance of p-type copper phthalocyanine （CuPc） based organic field-effect transistors （OFETs） by employing a thin para-quaterphenyl （p-4p） film and simultane- ously applying V205 to the source/drain regions. The p-4p layer was inserted between the insulating layer and the active layer, and V205 layer was added between CuPc and A1 in the source-drain （S/D） area. As a result, the field- effect saturation mobility and on/off current ratio of the optimized device were improved to 5 × 10-2 cm2/（V.s） and 104, respectively. We believe that because p-4p could induce CuPc to form a highly oriented and continuous film, this resulted in the better injection and transport of the carriers. Moreover, by introducing the V205 electrode＇s modified layers, the height of the carrier injection barrier could be effectively tuned and the contact resistance could be reduced.
文摘In vertical channel transistors(VCTs),source/drain ion implantation(I/I)represents a significant technical challenge due to inherent three-dimensional structural constraints,which induce complications such as difficulties in dummy gate forma-tion and shadowing effects of I/I.This article systematically investigates the impact of different implantation conditions on the performance of VCTs with and without dummy gates through TCAD simulation.It reveals the significant role of the lightly doped regions(LDRs)naturally formed due to ion implantation in source/drain of VCTs.Furthermore,it was found that VCT with-out dummy gates can achieve an approximately 27%increase in on-state current(Ion)under the same implantation conditions,and can greatly simplify the process flow and reduce costs.Finally,N-type and P-type VCTs were successfully fabricated using this implantation method.
文摘m thin-film fully-depleted SOI CMOS devices with elevated source/drain structure are fabricated by a novel technology.Key process technologies are demonstrated.The devices have quasi-ideal subthreshold properties;the subthreshold slope of nMOSFETs is 65mV/decade,while that of pMOSFETs is 69mV/decade.The saturation current of 1.2μm nMOSFETs is increased by 32% with elevated source/drain structure,and that of 1.2μm pMOSFETs is increased by 24%.The per-stage propagation delay of 101-stage fully-depleted SOI CMOS ring oscillator is 75ps with 3V supply voltage.
文摘The effects of source-drain underlaps on the performance of a top gate silicon nanowire on insulator transistor are studied using a three dimensional(3D) self-consistent Poisson-Schrodinger quantum simulation. Voltage-controlled tunnel barrier is the device transport physics. The off current, the on/off current ratio, and the inverse subthreshold slope are improved while the on current is degraded with underlap. The physics behind this behavior is the modulation of a tunnel barrier with underlap. The underlap primarily affects the tunneling component of drain current. About 50% contribution to the gate capacitance comes from the fringing electric fields emanating from the gate metal to the source and drain. The gate capacitance reduces with underlap, which should reduce the intrinsic switching delay and increase the intrinsic cut-off frequency. However, both the on current and the transconductance reduce with underlap, and the consequence is the increase of delay and the reduction of cut-off frequency.
基金Supported by the National Natural Science Foundation of China under Grant No 61504120the Zhejiang Provincial Natural Science Foundation of China under Grant No LR18F040001the Fundamental Research Funds for the Central Universities
文摘Ge complementary tunneling field-effect transistors（TFETs） are fabricated with the NiGe metal source/drain（S/D） structure. The dopant segregation method is employed to form the NiGe/Ge tunneling junctions of sufficiently high Schottky barrier heights. As a result, the Ge p-and n-TFETs exhibit decent electrical properties of large ON-state current and steep sub-threshold slope（S factor）. Especially, I_d of 0.2 μA/μm is revealed at V_g-V_（th） = V_d = ±0.5 V for Ge pTFETs,with the S factor of 28 mV/dec at 7 K.
文摘Fin field-effect transistor(FinFET)technology has been introduced to the mainstream complementary metal-oxide semiconductor(CMOS)manufacturing for low-power and highperformance applications.However,advanced FinFET nodes are facing significant challenges to enhance the device performance due to the increasingly prominent parasitic resistance and capacitance.In this study,for the first time,we demonstrate methods of enhancing p-channel FinFET(pFET)performance on a fully integrated advanced FinFET platform via source/drain(S/D)cavity structure optimization.By modulating the cavity depth and proximity around the optimal reference point,we show that the trade-off between the S/D resistance and short channel effect,as well as the impact on the parasitic capacitance must be considered for the S/D cavity structure optimization.An extra process knob of applying cavity implant on the desired cavity structure was also demonstrated to modify the S/D junction profile for device performance enhancement.
基金NSFC(90923027 and 51050110137)The Fundamental Research Funds for Central Universitie
文摘Effect of heat source sliding contact on the CoPtCr-based magnetic recording disk was investigated.A tribo-test of the disk with low load heat source and the scan of disk with magnetic head were sequentially carried out.Then disk samples in the contact area were observed by atomic force microscopy(AFM)and magnetic force microscopy(MFM).A finite element model using thermomechanical coupling was developed to calculate the mechanical and thermal response of the disk under heat source sliding contact based on the experimental results.It was found that data loss load under sliding contact with a heat source was far less than that without a heat source,and mechanical scratches and demagnetization did not occur in the data loss area under the experimental conditions.The finite element analysis(FEA)results indicate that the thin surface DLC coating has more significant effect on the mechanical response than the thermal response of the magnetic layer.
文摘Source-contacting gas, which is also called basin-center gas, deep basin gas, is the tight-sand gas accumulation contacting closely to its source rocks. Having different accumulation mechanisms from conventional gas reservoirs that are formed by replacement way, the typical source-contacting gas reservoirs are formed by piston-typed migration forward way. Source-contacting gas accumulations exhibit a series of distinctly mechanic characteristics. According to the valid combination of these characteristics, the estimation for the type of discovered gas reservoirs or distributions of source-contacting gas reservoirs can be forecasted. The source-contacting gas is special for having no edge water or bottom water for gas and complicated gas-water relationships, which emphasizes the intimate association of reservoir rocks with source rocks, which is called the root of the gas reservoir. There are many basins having the mechanic conditions for source-contacting gas accumulations in China, which can be divided into three regions. Most of the basins with favorable accumulation conditions are located mainly in the central and western China. According to the present data, basins having source-contacting gas accumulations in China can be divided into three types, accumulation conditions and configuration relationships are the best in type A basins and they are the larger basins in central China. Type B basins with plain accumulation conditions exist primarily in eastern China and also the basins in western China. Accumulation conditions and exploration futures are worse in type C basins, which refer mainly to the small basins in southern China and China Sea basins. Main source-contacting gas basins in China are thoroughly discussed in this paper and the distribution patterns of source-contacting gas in five huge basins are discussed and forecasted.
基金Project supported by the National Natural Science Foundation of China （Grant No 60506009）.
文摘In this paper, we propose a novel Schottky barrier MOSFET structure, in which the silicide source/drain is designed on the buried metal （SSDOM）. The source/drain region consists of two layers of silicide materials. Two Schottky barriers are formed between the silicide layers and the silicon channel. In the device design, the top barrier is lower and the bottom is higher. The lower top contact barrier is to provide higher on-state current, and the higher bottom contact barrier to reduce the off-state current. To achieve this, ErSi is proposed for the top silicide and CoSi2 for the bottom in the n-channel ease. The 50 nm n-channel SSDOM is thus simulated to analyse the performance of the SSDOM device. In the simulations, the top contact barrier is 0.2e V （for ErSi） and the bottom barrier is 0.6 eV （for CoSi2）. Compared with the corresponding conventional Schottky barrier MOSFET structures （CSB）, the high on-state current of the SSDOM is maintained, and the off-state current is efficiently reduced. Thus, the high drive ability （1.2 mA/μm at Vds = 1 V, Vgs = 2 V） and the high Ion/Imin ratio （10^6） are both achieved by applying the SSDOM structure.
基金Project supported by the National Natural Science Foundation of China(Grant No.61204086)
文摘A new modified Angelov current–voltage characteristic model equation is proposed to improve the drain–source current（Ids） simulation of an Al Ga N/Ga N-based（gallium nitride） high electron mobility transistor（Al Ga N/Ga N-based HEMT） at high power operation. Since an accurate radio frequency（RF） current simulation is critical for a correct power simulation of the device, in this paper we propose a method of Al Ga N/Ga N high electron mobility transistor（HEMT）nonlinear large-signal model extraction with a supplemental modeling of RF drain–source current as a function of RF input power. The improved results of simulated output power, gain, and power added efficiency（PAE） at class-AB quiescent bias of Vgs =-3.5 V, Vds= 30 V with a frequency of 9.6 GHz are presented.
基金the National Key Research and Development Program of China(Grant No.2016YFA0200503).
文摘We investigate the influence of source and drain bias voltages(V_(DS))on the quantum sub-band transport spectrum in the 10-nm width N-typed junctionless nanowire transistor at the low temperature of 6 K.We demonstrate that the transverse electric field introduced from V_(DS) has a minor influence on the threshold voltage of the device.The transverse electric field plays the role of amplifying the gate restriction effect of the channel.The one-dimensional(1D)-band dominated transport is demonstrated to be modulated by V_(DS) in the saturation region and the linear region,with the sub-band energy levels in the channel(E_(channel))intersecting with Fermi levels of the source(E_(fS))and the drain(E_(fD))in turn as V_(g) increases.The turning points from the linear region to the saturation region shift to higher gate voltages with V_(DS) increase because the higher Fermi energy levels of the channel required to meet the situation of E_(fD)=E_(channel).We also find that the bias electric field has the effect to accelerate the thermally activated electrons in the channel,equivalent to the effect of thermal temperature on the increase of electron energy.Our work provides a detailed description of the bias-modulated quantum electronic properties,which will give a more comprehensive understanding of transport behavior in nanoscale devices.
基金supported by the Science and Engineering Research Board(SERB),Department of Science and Technology,Ministry of Human Resource and Development,Government of India under Young Scientist Research(Grant No.SB/FTP/ETA-415/2012)
文摘In this paper, a surface potential based threshold voltage model of fully-depleted（FD） recessed-source/drain（Re-S/D）silicon-on-insulator（SOI） metal-oxide semiconductor field-effect transistor（MOSFET） is presented while considering the effects of high-k gate-dielectric material induced fringing-field. The two-dimensional（2D） Poisson＇s equation is solved in a channel region in order to obtain the surface potential under the assumption of the parabolic potential profile in the transverse direction of the channel with appropriate boundary conditions. The accuracy of the model is verified by comparing the model＇s results with the 2D simulation results from ATLAS over a wide range of channel lengths and other parameters,including the dielectric constant of gate-dielectric material.
基金Project supported by the National Natural Science Foundation of China (Grant No. 11174182)the Specialized Research Fund for the Doctoral Program of Higher Education of China (Grant No. 20110131110005)
文摘Rectangular Schottky drain AlGaN/AlN/GaN heterostructure field-effect transistors （HFETs） with different gate contact areas and conventional AlGaN/AlN/GaN HFETs as control were both fabricated with same size. It was found there is a significant difference between Schottky drain AlGaN/AlN/GaN HFETs and the control group both in drain series resistance and in two-dimensional electron gas （2DEG） electron mobility in the gate–drain channel. We attribute this to the different influence of Ohmic drain contacts and Schottky drain contacts on the strained AlGaN barrier layer. For conventional AlGaN/AlN/GaN HFETs, annealing drain Ohmic contacts gives rise to a strain variation in the AlGaN barrier layer between the gate contacts and the drain contacts, and results in strong polarization Coulomb field scattering in this region. In Schottky drain AlGaN/AlN/GaN HFETs, the strain in the AlGaN barrier layer is distributed more regularly.
基金This work was supported by the Major State Basic Research Development Program of China, under Contract 51327010101.
文摘Two-dimensional DC and small-signal analysis of gate-to-source scaling effects in SiC-based high-power field-effect transistors have been performed in this paper. The simulation results show that a downscaling of gate-to-source distance can improve device performance, i.e. enhancing drain current, transconductance, and maximum oscillation frequency. This is associated with the peculiar dynamic of electrons in SiC MESFETs, which lead to a linear velocity regime in the source access region. The variations of gate-to-source capacitance, gate-to-drain capacitance, and cut-off frequency with respect to the change in gate-to-source length have also been studied in detail.
文摘为解决碳化硅金属氧化物半导体场效应晶体管(SiC Metal Oxide Semiconductor Field Effect Transistor,SiC MOSFET)硬开关故障(Hard Switch Fault,HSF)、负载故障(Fault Under Load,FUL)和过载故障(OverLoad fault,OL)的问题,本文提出了一种基于SiC MOSFET漏极电压和源极电压检测的过流保护方法(OverCurrent Protection method based on the Drain-voltage and Source-voltage Detection,DSD-OCP).该方法通过检测电路实时监控SiC MOSFET的漏极电压和源极电压来准确识别短路故障和过载故障,并利用驱动电路控制SiC MOSFET的开通和关断,从而实现快速短路保护和自适应过载保护,同时还集成软关断功能.基于0.5μm双极型-互补金属氧化物半导体-双扩散金属氧化物半导体(Bipolar-CMOS-DMOS,BCD)工艺,设计了DSD-OCP电路并进行流片,芯片面积为2.8 mm^(2).采用研制的芯片搭建1200 V/80 mΩSiC MOSFET测试平台,并验证了DSD-OCP方法的有效性.实验结果表明,SiC MOSFET在DSD-OCP芯片保护下的HSF和FUL持续时间分别为88 ns和105 ns.在不同母线电压下,DSD-OCP芯片能够为SiC MOSFET提供自适应的过载保护.因DSD-OCP芯片具有软关断功能,SiC MOSFET在过流保护时的漏极电压过冲不超过110 V.
