A two-stage driving circuit of a one-chip TFT-LCD driver IC for portable electronic devices is proposed. The driving buffers of the new circuit are built in the γ-correction circuit rather than in the source driver. ...A two-stage driving circuit of a one-chip TFT-LCD driver IC for portable electronic devices is proposed. The driving buffers of the new circuit are built in the γ-correction circuit rather than in the source driver. The power consumption,die area, and driving capability of the driving circuit are discussed in detail. For a two-stage driving circuit with 13 driving buffers, the settling time of the driving voltage within 0.2% error is about 19.2μs when 396 pixel-loads are driven by the same grayscale voltage. The quiescent current of the whole driving circuit is 518μ~A,and the power consumption can be reduced by 77%. The proposed driving circuit is successfully applied in a 132RGB × 176-dot,260k color one-chip driver IC developed by us for the TFT-LCD of mobile phone, and it can also be used in other portable electronic devices, such as PDAs and digital cameras.展开更多
Four-level pulse amplitude modulation(PAM4)signals,recognized for enhanced energy efficiency and spectral utilization compared with non-return-to-zero(NRZ)counterparts,have been adopted in multiple high-speed serializ...Four-level pulse amplitude modulation(PAM4)signals,recognized for enhanced energy efficiency and spectral utilization compared with non-return-to-zero(NRZ)counterparts,have been adopted in multiple high-speed serializer/deserializer(SerDes)standards,but NRZ modulation remains predominant in industrial applications.This paper introduces a UMC 28 nm CMOS-based parallel configurable forward feedback equalization(FFE)dual-mode high-speed SerDes transmitter supporting 7-bit resolution with data rates of 56 Gb∙s^(-1)NRZ and 112 Gb∙s^(-1)PAM4,utilizing a hybrid architecture that integrates digital signal processing(DSP)with digital-to-analog conversion(DAC).The design processes parallel input signals and eight stored 8-bit tap coefficients through a configurable FFE multiplier module and parallel carry adder module,while achieving low-power serialization via low-speed 16∶4 multiplexers(MUXs)with two different 2∶1 MUXs and high-speed 4∶1 MUXs.A source series termination(SST)output network structure enhances lower power dissipation and higher output swing.Simulation results show that,under a 1.05 V supply voltage and a channel loss of 19.21 dB at 28 GHz,the output 56 Gb∙s^(-1)NRZ eye diagram has an eye height of 70.11 mV and an eye width of 12.16 ps(0.68 UI).The output 112 Gb∙s^(-1)PAM4 eye diagram has an eye height of 20.07 mV and an eye width of 7.49 ps(0.42 UI).The layout area of the dual-mode transmitter is 0.079 mm^(2),and the total circuit power consumption is 74.48 mW(energy efficiency is 1.33/0.67 pJ∙bit-1).展开更多
文摘A two-stage driving circuit of a one-chip TFT-LCD driver IC for portable electronic devices is proposed. The driving buffers of the new circuit are built in the γ-correction circuit rather than in the source driver. The power consumption,die area, and driving capability of the driving circuit are discussed in detail. For a two-stage driving circuit with 13 driving buffers, the settling time of the driving voltage within 0.2% error is about 19.2μs when 396 pixel-loads are driven by the same grayscale voltage. The quiescent current of the whole driving circuit is 518μ~A,and the power consumption can be reduced by 77%. The proposed driving circuit is successfully applied in a 132RGB × 176-dot,260k color one-chip driver IC developed by us for the TFT-LCD of mobile phone, and it can also be used in other portable electronic devices, such as PDAs and digital cameras.
基金Supported by the National Key R&D Program Broadband Communications and New Network Key Special Project(No.2019YFB1803600).
文摘Four-level pulse amplitude modulation(PAM4)signals,recognized for enhanced energy efficiency and spectral utilization compared with non-return-to-zero(NRZ)counterparts,have been adopted in multiple high-speed serializer/deserializer(SerDes)standards,but NRZ modulation remains predominant in industrial applications.This paper introduces a UMC 28 nm CMOS-based parallel configurable forward feedback equalization(FFE)dual-mode high-speed SerDes transmitter supporting 7-bit resolution with data rates of 56 Gb∙s^(-1)NRZ and 112 Gb∙s^(-1)PAM4,utilizing a hybrid architecture that integrates digital signal processing(DSP)with digital-to-analog conversion(DAC).The design processes parallel input signals and eight stored 8-bit tap coefficients through a configurable FFE multiplier module and parallel carry adder module,while achieving low-power serialization via low-speed 16∶4 multiplexers(MUXs)with two different 2∶1 MUXs and high-speed 4∶1 MUXs.A source series termination(SST)output network structure enhances lower power dissipation and higher output swing.Simulation results show that,under a 1.05 V supply voltage and a channel loss of 19.21 dB at 28 GHz,the output 56 Gb∙s^(-1)NRZ eye diagram has an eye height of 70.11 mV and an eye width of 12.16 ps(0.68 UI).The output 112 Gb∙s^(-1)PAM4 eye diagram has an eye height of 20.07 mV and an eye width of 7.49 ps(0.42 UI).The layout area of the dual-mode transmitter is 0.079 mm^(2),and the total circuit power consumption is 74.48 mW(energy efficiency is 1.33/0.67 pJ∙bit-1).
