Soft errors have become a critical challenge as a result of technology scaling. Existing circuit-hardening techniques are commonly associated with prohibitive overhead of performance, area, and power. However,evaluati...Soft errors have become a critical challenge as a result of technology scaling. Existing circuit-hardening techniques are commonly associated with prohibitive overhead of performance, area, and power. However,evaluating the influence of soft errors in Flip-Flops(FFs) on the failure of circuit is a difficult verification problem.Here, we proposed a novel flip-flop soft-error failure rate analysis methodology using a formal method with respect to application behaviors. Approach and optimization techniques to implement the proposed methodology based on the given formula using Sequential Equivalence Checking(SEC) are introduced. The proposed method combines the advantage of formal technique-based approaches in completeness and the advantage of application behaviors in accuracy to differentiate vulnerability of components. As a result, the FFs in a circuit are sorted by their failure rates, and designers can use this information to perform optimal hardening of selected sequential components against soft errors. Experimental results of an implementation of a SpaceWire end node and the largest ISCAS’89 benchmark sequential circuits indicate the feasibility and potential scalability of our approach. A case study on an instruction decoder of a practical 32-bit microprocessor demonstrates the applicability of our method.展开更多
With the decrease of the device size,soft error induced by various particles becomes a serious problem for advanced CMOS technologies.In this paper,we review the evolution of two main aspects of soft error-SEU and SET...With the decrease of the device size,soft error induced by various particles becomes a serious problem for advanced CMOS technologies.In this paper,we review the evolution of two main aspects of soft error-SEU and SET,including the new mechanisms to induced SEUs,the advances of the MCUs and some newly observed phenomena of the SETs.The mechanisms and the trends with downscaling of these issues are briefly discussed.We also review the hardening strategies for different types of soft errors from different perspective and present the challenges in testing,modeling and hardening assurance of soft error issues we have to address in the future.展开更多
To predict the soft error rate for applications, it is essential to study the energy dependence of the single-event-upset(SEU) cross-section. In this work, we present a direct measurement of the SEU cross-section with...To predict the soft error rate for applications, it is essential to study the energy dependence of the single-event-upset(SEU) cross-section. In this work, we present a direct measurement of the SEU cross-section with the Back-n white neutron source at the China Spallation Neutron Source. The measured cross section is consistent with the soft error data from the manufacturer and the result suggests that the threshold energy of the SEU is about 0.5 Me V, which confirms the statement in Iwashita’s report that the threshold energy for neutron soft error is much below that of the(n, α) cross-section of silicon.In addition, an index of the effective neutron energy is suggested to characterize the similarity between a spallation neutron beam and the standard atmospheric neutron environment.展开更多
基金supported by the National Key Basic R&D Program (973) of China (No. 2017YFB1001802)
文摘Soft errors have become a critical challenge as a result of technology scaling. Existing circuit-hardening techniques are commonly associated with prohibitive overhead of performance, area, and power. However,evaluating the influence of soft errors in Flip-Flops(FFs) on the failure of circuit is a difficult verification problem.Here, we proposed a novel flip-flop soft-error failure rate analysis methodology using a formal method with respect to application behaviors. Approach and optimization techniques to implement the proposed methodology based on the given formula using Sequential Equivalence Checking(SEC) are introduced. The proposed method combines the advantage of formal technique-based approaches in completeness and the advantage of application behaviors in accuracy to differentiate vulnerability of components. As a result, the FFs in a circuit are sorted by their failure rates, and designers can use this information to perform optimal hardening of selected sequential components against soft errors. Experimental results of an implementation of a SpaceWire end node and the largest ISCAS’89 benchmark sequential circuits indicate the feasibility and potential scalability of our approach. A case study on an instruction decoder of a practical 32-bit microprocessor demonstrates the applicability of our method.
基金supported by the National Natural Science Foundation of China(Grant No.11175138)the Specialized Research Fund for the Doctoral Program of Higher Education of China(Grant No.20100201110018)+1 种基金the Key Program of the National Natural Science Foundation of China(Grant No.11235008)the State Key Laboratory Program(Grant No.20140134)
文摘With the decrease of the device size,soft error induced by various particles becomes a serious problem for advanced CMOS technologies.In this paper,we review the evolution of two main aspects of soft error-SEU and SET,including the new mechanisms to induced SEUs,the advances of the MCUs and some newly observed phenomena of the SETs.The mechanisms and the trends with downscaling of these issues are briefly discussed.We also review the hardening strategies for different types of soft errors from different perspective and present the challenges in testing,modeling and hardening assurance of soft error issues we have to address in the future.
基金supported by the National Natural Science Foundation of China (Grant Nos. 2032165 and 62004158)the National Key Scientific Instrument and Equipment Development Project of China (Grant No. 52127817)+1 种基金the State Key Laboratory of Particle Detection and Electronics (Grant Nos. SKLPDE-ZZ-201801 and SKLPDE-ZZ-202008)the Special Funds for Science and Technology Innovation Strategy of Guangdong Province, China (Grant No. 2018A0303130030)。
文摘To predict the soft error rate for applications, it is essential to study the energy dependence of the single-event-upset(SEU) cross-section. In this work, we present a direct measurement of the SEU cross-section with the Back-n white neutron source at the China Spallation Neutron Source. The measured cross section is consistent with the soft error data from the manufacturer and the result suggests that the threshold energy of the SEU is about 0.5 Me V, which confirms the statement in Iwashita’s report that the threshold energy for neutron soft error is much below that of the(n, α) cross-section of silicon.In addition, an index of the effective neutron energy is suggested to characterize the similarity between a spallation neutron beam and the standard atmospheric neutron environment.
