The reverse snapback phenomena （RSP） on I-V characteristics of static induction thyristors （SITH） are physically researched. The I-V curves of the power SITH exhibit reverse snapback phenomena, and even turn to th...The reverse snapback phenomena （RSP） on I-V characteristics of static induction thyristors （SITH） are physically researched. The I-V curves of the power SITH exhibit reverse snapback phenomena, and even turn to the conducting-state,when the anode voltage in the forward blocking-state is increased to a critical value. The RSP I-V characteristics of the power SITH are analyzed in terms of operating mechanism, double carrier injection effect, space charge effect, electron-hole plasma in the channel, and the variation in carrier lifetime. The reverse snapback mechanism is theoretically pro- posed and the mathematical expressions to calculate the voltage and current values at the snapback point are presented. The computing results are compared with the experiment values.展开更多
By measurement,we investigate the characteristics and location of gate oxide damage induced by snapback stress. The damage incurred during stress causes device degradation that follows an approximate power law with st...By measurement,we investigate the characteristics and location of gate oxide damage induced by snapback stress. The damage incurred during stress causes device degradation that follows an approximate power law with stress time. Oxide traps generated by stress will cause the increase of stress-induced leakage current and the decrease of Qbd （charge to breakdown）,and it may also cause the degradation of off-state drain leakage current. Stress-induced gate oxide damage is located not only in the drain side but also in the source side. The tertiary electrons generated by hot holes move toward Si-SiO2 interface under the electrical field toward the substrate,which explains the source side gate oxide damage.展开更多
A novel reverse-conducting insulated-gate bipolar transistor （RC-IGBT） featuring a floating P-plug is proposed. The P-plug is embedded in the n-buffer layer to obstruct the electron current from flowing directly to ...A novel reverse-conducting insulated-gate bipolar transistor （RC-IGBT） featuring a floating P-plug is proposed. The P-plug is embedded in the n-buffer layer to obstruct the electron current from flowing directly to the n-collector, which achieves the hole emission from the p-collector at a small collector size and suppresses the snapback effectively. More- over, the current is uniformly distributed in the whole wafer at both IGBT mode and diode mode, which ensures the high temperature reliability of the RC-IGBT. Additionally, the P-plug acts as the base of the N-buffer/P-float/N-buffer transistor, which can be activated to extract the excessive carriers at the turn-off process. As the the simulation results show, for the proposed RC-IGBT, it achieves almost snapback-free output characteristics with a uniform current density and a uniform temperature distribution, which can greatly increase the reliability of the device.展开更多
A reverse-conducting lateral insulated-gate bipolar transistor （NI.2-LltJlS｜） with a trench oxide layer （IUL）, teaturlng a vertical N-buffer and P-collector is proposed. Firstly, the TOL enhances both of the surf...A reverse-conducting lateral insulated-gate bipolar transistor （NI.2-LltJlS｜） with a trench oxide layer （IUL）, teaturlng a vertical N-buffer and P-collector is proposed. Firstly, the TOL enhances both of the surface and bulk electric fields of the N-drift region, thus the breakdown voltage （BV） is improved. Secondly, the vertical N-buffer layer increases the voltage drop VpN of the P-collector/N-buffer junction, thus the snapback is suppressed. Thirdly, the P-body and the vertical N-buffer act as the anode and the cathode, respectively, to conduct the reverse current, thus the inner diode is integrated. As shown by the simulation results, the proposed RC-LIGBT exhibits trapezoidal electric field distribution with BV of 342.4 V, which is increased by nearly 340% compared to the conventional RC-LIGBT with triangular electric fields of 100.2 V. Moreover, the snapback is eliminated by the vertical N-buffer layer design, thus the reliability of the device is improved.展开更多
A novel shorted anode lateral-insulated gate bipolar transistor(SA LIGBT)with snapback-free characteristic is proposed and investigated.The device features a controlled barrier V_(barrier)and resistance R_(SA)in anode...A novel shorted anode lateral-insulated gate bipolar transistor(SA LIGBT)with snapback-free characteristic is proposed and investigated.The device features a controlled barrier V_(barrier)and resistance R_(SA)in anode,named CBR LIGBT.The electron barrier is formed by the P-float/N-buffer junction,while the anode resistance includes the polysilicon layer and N-float.At forward conduction stage,the V_(barrier)and R_(SA)can be increased by adjusting the doping of the P-float and polysilicon layer,respectively,which can suppress the unipolar mode to eliminate the snapback.At turn-off stage,the low-resistance extraction path(N-buffer/P-float/polysilicon layer/N-float)can quickly extract the electrons in the N-drift,which can effectively accelerate the turn-off speed of the device.The simulation results show that at the same V_(on) of 1.3 V,the E_(off)of the CBR LIGBT is reduced by 85%,73%,and 59.6%compared with the SSA LIGBT,conventional LIGBT,and TSA LIGBT,respectively.Additionally,at the same Eoffof 1.5 m J/cm^(2),the CBR LIGBT achieves the lowest V_(on) of 1.1 V compared with the other LIGBTs.展开更多
Work study is an area of construction production rationalization in which with scientific, logical, holistic and system analysis methods of the process we gain optimum in way of work and time of work. Chronometry meth...Work study is an area of construction production rationalization in which with scientific, logical, holistic and system analysis methods of the process we gain optimum in way of work and time of work. Chronometry method is one of the work study methods which is appropriate for recording shorter cyclic processes and is based on statistical sampling theory. Determination of cyclic times and work performances of standard cyclic construction machines （SCCM） is one of key assumptions of dynamic planning of machine work on every construction site. Calculation methods of SCCM work performances arc one of basic research objects in the field of construction organization and technology. Study shows applied chronometry method in work of standard cyclic construction machine. Goal of this study is to accomplish regulation through measured time cycle and compare measured effects with effects obtained with standard methodology of calculating hydraulic excavator practical achievement for gaining regulation in order to determine main reasons which effect work performance on site.展开更多
Gate-grounded NMOS （GGNMOS） devices with different device dimensions and layout floorplans have been designed and fabricated in 0.13-μm silicide CMOS technology. The snapback characteristics of these GGN-MOS device...Gate-grounded NMOS （GGNMOS） devices with different device dimensions and layout floorplans have been designed and fabricated in 0.13-μm silicide CMOS technology. The snapback characteristics of these GGN-MOS devices are measured using the transmission line pulsing （TLP） measurement technique. The relationships between snapback parameters and layout parameters are shown and analyzed. A TCAD device simulator is used to explain these relationships. From these results, the circuit designer can predict the behavior of the GGNMOS devices under high ESD current stress, and design area-efficient ESD protection circuits to sustain the required ESD level. Optimized layout rules for ESD protection in 0.13-μm silicide CMOS technology are also presented.展开更多
Criterion for the second snapback of an LDMOS with an embedded SCR is given based on parasitic parameter analysis.According to this criterion,three typical structures are compared by numerical simulation and structura...Criterion for the second snapback of an LDMOS with an embedded SCR is given based on parasitic parameter analysis.According to this criterion,three typical structures are compared by numerical simulation and structural parameters which influence the second snapback are also analyzed to optimize the ESD characteristics. Experimental data showed that,as the second snapback voltage decreased from 25.4 to 8.1 V,the discharge ability of the optimized structure increased from 0.57 to 3.1 A.展开更多
A physically based equation for predicting required p-emitter length of a snapback-free reverse- conducting insulated gate bipolar transistor （RC-IGBT） with field-stop structure is proposed. The n-buffer resis- tanc...A physically based equation for predicting required p-emitter length of a snapback-free reverse- conducting insulated gate bipolar transistor （RC-IGBT） with field-stop structure is proposed. The n-buffer resis- tances above the p-emitter region with anode geometries of linear strip, circular and annular type are calculated, and based on this, the minimum p-emitter lengths of those three geometries are given and verified by simulation. It is found that good agreement was achieved between the numerical calculation and simulation results. Moreover, the calculation results show that the annular case needs the shortest p-emitter length for RC-IGBT to be snapback-free.展开更多
文摘The reverse snapback phenomena （RSP） on I-V characteristics of static induction thyristors （SITH） are physically researched. The I-V curves of the power SITH exhibit reverse snapback phenomena, and even turn to the conducting-state,when the anode voltage in the forward blocking-state is increased to a critical value. The RSP I-V characteristics of the power SITH are analyzed in terms of operating mechanism, double carrier injection effect, space charge effect, electron-hole plasma in the channel, and the variation in carrier lifetime. The reverse snapback mechanism is theoretically pro- posed and the mathematical expressions to calculate the voltage and current values at the snapback point are presented. The computing results are compared with the experiment values.
文摘By measurement,we investigate the characteristics and location of gate oxide damage induced by snapback stress. The damage incurred during stress causes device degradation that follows an approximate power law with stress time. Oxide traps generated by stress will cause the increase of stress-induced leakage current and the decrease of Qbd （charge to breakdown）,and it may also cause the degradation of off-state drain leakage current. Stress-induced gate oxide damage is located not only in the drain side but also in the source side. The tertiary electrons generated by hot holes move toward Si-SiO2 interface under the electrical field toward the substrate,which explains the source side gate oxide damage.
基金Project supported by the National Science and Technology Major Project, China （Grant No. 2011ZX02504-003）, the National Natural Science Foundation of China （Grant No. 61076082）, and the Fundamental Research Funds for the Central Universities, China （Grant No. ZYGX2011 J024）.
文摘A novel reverse-conducting insulated-gate bipolar transistor （RC-IGBT） featuring a floating P-plug is proposed. The P-plug is embedded in the n-buffer layer to obstruct the electron current from flowing directly to the n-collector, which achieves the hole emission from the p-collector at a small collector size and suppresses the snapback effectively. More- over, the current is uniformly distributed in the whole wafer at both IGBT mode and diode mode, which ensures the high temperature reliability of the RC-IGBT. Additionally, the P-plug acts as the base of the N-buffer/P-float/N-buffer transistor, which can be activated to extract the excessive carriers at the turn-off process. As the the simulation results show, for the proposed RC-IGBT, it achieves almost snapback-free output characteristics with a uniform current density and a uniform temperature distribution, which can greatly increase the reliability of the device.
基金Project supported by the National Natural Science Foundation of China(Grant No.61604027)the Basic and Advanced Technology Research Project of Chongqing Municipality,China(Grant No.cstc2016jcyj A1923)+3 种基金the Scientific and Technological Research Foundation of Chongqing Municipal Education Commission,China(Grant No.KJ1500404)the Youth Natural Science Foundation of Chongqing University of Posts and Telecommunications,China(Grant Nos.A2015-50 and A2015-52)the Chongqing Key Laboratory Improvement Plan,China(Chongqing Key Laboratory of Photo Electronic Information Sensing and Transmitting Technology)(Grant No.cstc2014pt-sy40001)the University Innovation Team Construction Plan Funding Project of Chongqing,China(Architecture and Core Technologies of Smart Medical System)(Grant No.CXTDG201602009)
文摘A reverse-conducting lateral insulated-gate bipolar transistor （NI.2-LltJlS｜） with a trench oxide layer （IUL）, teaturlng a vertical N-buffer and P-collector is proposed. Firstly, the TOL enhances both of the surface and bulk electric fields of the N-drift region, thus the breakdown voltage （BV） is improved. Secondly, the vertical N-buffer layer increases the voltage drop VpN of the P-collector/N-buffer junction, thus the snapback is suppressed. Thirdly, the P-body and the vertical N-buffer act as the anode and the cathode, respectively, to conduct the reverse current, thus the inner diode is integrated. As shown by the simulation results, the proposed RC-LIGBT exhibits trapezoidal electric field distribution with BV of 342.4 V, which is increased by nearly 340% compared to the conventional RC-LIGBT with triangular electric fields of 100.2 V. Moreover, the snapback is eliminated by the vertical N-buffer layer design, thus the reliability of the device is improved.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61604027 and 61704016)the Fund from Chongqing Technology Innovation and Application Development(Key Industry Research and Development),China(Grant No.cstc2018jszx-cyzd0646)。
文摘A novel shorted anode lateral-insulated gate bipolar transistor(SA LIGBT)with snapback-free characteristic is proposed and investigated.The device features a controlled barrier V_(barrier)and resistance R_(SA)in anode,named CBR LIGBT.The electron barrier is formed by the P-float/N-buffer junction,while the anode resistance includes the polysilicon layer and N-float.At forward conduction stage,the V_(barrier)and R_(SA)can be increased by adjusting the doping of the P-float and polysilicon layer,respectively,which can suppress the unipolar mode to eliminate the snapback.At turn-off stage,the low-resistance extraction path(N-buffer/P-float/polysilicon layer/N-float)can quickly extract the electrons in the N-drift,which can effectively accelerate the turn-off speed of the device.The simulation results show that at the same V_(on) of 1.3 V,the E_(off)of the CBR LIGBT is reduced by 85%,73%,and 59.6%compared with the SSA LIGBT,conventional LIGBT,and TSA LIGBT,respectively.Additionally,at the same Eoffof 1.5 m J/cm^(2),the CBR LIGBT achieves the lowest V_(on) of 1.1 V compared with the other LIGBTs.
文摘Work study is an area of construction production rationalization in which with scientific, logical, holistic and system analysis methods of the process we gain optimum in way of work and time of work. Chronometry method is one of the work study methods which is appropriate for recording shorter cyclic processes and is based on statistical sampling theory. Determination of cyclic times and work performances of standard cyclic construction machines （SCCM） is one of key assumptions of dynamic planning of machine work on every construction site. Calculation methods of SCCM work performances arc one of basic research objects in the field of construction organization and technology. Study shows applied chronometry method in work of standard cyclic construction machine. Goal of this study is to accomplish regulation through measured time cycle and compare measured effects with effects obtained with standard methodology of calculating hydraulic excavator practical achievement for gaining regulation in order to determine main reasons which effect work performance on site.
基金supported by the National Natural Science Foundation of China(Nos.60773081,60777018)the AM Foundation by Science and Technology Commission of Shanghai Municipality(No.087009741000)the SDC Project by Science and Technology Commission of Shanghai Municipality(Nos.08706201800,077062008,08706201000)
文摘Gate-grounded NMOS （GGNMOS） devices with different device dimensions and layout floorplans have been designed and fabricated in 0.13-μm silicide CMOS technology. The snapback characteristics of these GGN-MOS devices are measured using the transmission line pulsing （TLP） measurement technique. The relationships between snapback parameters and layout parameters are shown and analyzed. A TCAD device simulator is used to explain these relationships. From these results, the circuit designer can predict the behavior of the GGNMOS devices under high ESD current stress, and design area-efficient ESD protection circuits to sustain the required ESD level. Optimized layout rules for ESD protection in 0.13-μm silicide CMOS technology are also presented.
基金Project supported by the Analog Devices Inc and the National Natural Science Foundation of China(No.60906038)
文摘Criterion for the second snapback of an LDMOS with an embedded SCR is given based on parasitic parameter analysis.According to this criterion,three typical structures are compared by numerical simulation and structural parameters which influence the second snapback are also analyzed to optimize the ESD characteristics. Experimental data showed that,as the second snapback voltage decreased from 25.4 to 8.1 V,the discharge ability of the optimized structure increased from 0.57 to 3.1 A.
基金Project supported by the Fundamental Research Funds for the Central Universities(No.E022050205)the National Natural Science Foundation of China(No.51237001)
文摘A physically based equation for predicting required p-emitter length of a snapback-free reverse- conducting insulated gate bipolar transistor （RC-IGBT） with field-stop structure is proposed. The n-buffer resis- tances above the p-emitter region with anode geometries of linear strip, circular and annular type are calculated, and based on this, the minimum p-emitter lengths of those three geometries are given and verified by simulation. It is found that good agreement was achieved between the numerical calculation and simulation results. Moreover, the calculation results show that the annular case needs the shortest p-emitter length for RC-IGBT to be snapback-free.
