This paper quantitatively discusses the influence of well contact on single-event transient(SET)in sub-20 nm FinFET by two-photon absorption(TPA)pulse laser.Two groups of inverter chains were designed to investigate t...This paper quantitatively discusses the influence of well contact on single-event transient(SET)in sub-20 nm FinFET by two-photon absorption(TPA)pulse laser.Two groups of inverter chains were designed to investigate the impact of well contact distance on the FinFET process.The experimental results show that the SET pulse width has a bimodal symmetric distribution,which is different from that of a bulk planar CMOS device.To investigate the detailed mechanism of the phenomenon,a high-precision FinFET TCAD model was established,in which both Id-Vd and Id-Vg errors were less than 10%compared to the SPICE model provided by the commercial process.TCAD simulation under heavy ion injection showed the mechanism of the abnormal phenomenon,where the well contact plays a major role in charge collection at the near-well contact distance,while the source plays a major role at the far distance.This phenomenon is completely different from that of planar CMOS devices.This indicates that the SET mechanism becomes more complicated during the FinFET process.Therefore,more effective SET hardening methods should be investigated for FinFET.展开更多
We experimentally demonstrate that the dominant mechanism of single-event transients in silicon-germanium heterojunction bipolar transistors(SiGe HBTs)can change with decreasing temperature from+20℃to-180℃.This is a...We experimentally demonstrate that the dominant mechanism of single-event transients in silicon-germanium heterojunction bipolar transistors(SiGe HBTs)can change with decreasing temperature from+20℃to-180℃.This is accomplished by using a new well-designed cryogenic experimental system suitable for a pulsed-laser platform.Firstly,when the temperature drops from+20℃to-140℃,the increased carrier mobility drives a slight increase in transient amplitude.However,as the temperature decreases further below-140℃,the carrier freeze-out brings about an inflection point,which means the transient amplitude will decrease at cryogenic temperatures.To better understand this result,we analytically calculate the ionization rates of various dopants at different temperatures based on Altermatt's new incomplete ionization model.The parasitic resistivities with temperature on the charge-collection pathway are extracted by a two-dimensional(2D)TCAD process simulation.In addition,we investigate the impact of temperature on the novel electron-injection process from emitter to base under different bias conditions.The increase of the emitter-base junction's barrier height at low temperatures could suppress this electron-injection phenomenon.We have also optimized the built-in voltage equations of a high current compact model(HICUM)by introducing the impact of incomplete ionization.The present results and methods could provide a new reference for effective evaluation of single-event effects in bipolar transistors and circuits at cryogenic temperatures,and could provide a new evidence of the potential of SiGe technology in applications in extreme cryogenic environments.展开更多
As integrated circuits scale down in size, a single high-energy ion strike often affects multiple adjacent logic nodes.The so-called single-event transient（SET） pulse quenching induced by single-event charge sharing...As integrated circuits scale down in size, a single high-energy ion strike often affects multiple adjacent logic nodes.The so-called single-event transient（SET） pulse quenching induced by single-event charge sharing collection has been widely studied. In this paper, SET pulse quenching enhancement is found in dummy gate isolated adjacent logic nodes compared with that isolated by the common shallow trench isolation（STI）. The physical mechanism is studied in depth and this isolation technique is explored for SET mitigation in combinational standard cells. Three-dimensional（3D） technology computer-aided design simulation（TCAD） results show that this technique can achieve efficient SET mitigation.展开更多
In this study, we investigate the single-event transient（SET） characteristics of a partially depleted silicon-on-insulator（PDSOI） metal-oxide-semiconductor（MOS） device induced by a pulsed laser.We measure and an...In this study, we investigate the single-event transient（SET） characteristics of a partially depleted silicon-on-insulator（PDSOI） metal-oxide-semiconductor（MOS） device induced by a pulsed laser.We measure and analyze the drain transient current at the wafer level. The results indicate that the body-drain junction and its vicinity are more SET sensitive than the other regions in PD-SOI devices.We use ISE 3D simulation tools to analyze the SET response when different regions of the device are hit. Then, we discuss in detail the characteristics of transient currents and the electrostatic potential distribution change in devices after irradiation. Finally, we analyze the parasitic bipolar junction transistor（p-BJT） effect by performing both a laser test and simulations.展开更多
Based on 3 D-TCAD simulations, single-event transient(SET) effects and charge collection mechanisms in fully depleted silicon-on-insulator(FDSOI) transistors are investigated. This work presents a comparison between28...Based on 3 D-TCAD simulations, single-event transient(SET) effects and charge collection mechanisms in fully depleted silicon-on-insulator(FDSOI) transistors are investigated. This work presents a comparison between28-nm technology and 0.2-lm technology to analyze the impact of strike location on SET sensitivity in FDSOI devices. Simulation results show that the most SET-sensitive region in FDSOI transistors is the drain region near the gate. An in-depth analysis shows that the bipolar amplification effect in FDSOI devices is dependent on the strike locations. In addition, when the drain contact is moved toward the drain direction, the most sensitive region drifts toward the drain and collects more charge. This provides theoretical guidance for SET hardening.展开更多
Variation of substrate background doping will affect the charge collection of active and passive MOSFETs in complementary metal-oxide semiconductor （CMOS） technologies, which are significant for charge sharing, thus...Variation of substrate background doping will affect the charge collection of active and passive MOSFETs in complementary metal-oxide semiconductor （CMOS） technologies, which are significant for charge sharing, thus affecting the propagated single event transient pulsewidths in circuits. The trends of charge collected by the drain of a positive channel metal-oxide semiconductor （PMOS） and an N metal-oxide semiconductor （NMOS） are opposite as the substrate doping increases. The PMOS source will inject carriers after strike and the amount of charge injected will irlcrease as the substrate doping increases, whereas the source of the NMOS will mainly collect carriers and the source of the NMOS can also inject electrons when the substrate doping is light enough. Additionally, it indicates that substrate doping mainly affects the bipolar amplification component of a single-event transient current, and has little effect on the drift and diffusion. The change in substrate doping has a much greater effect on PMOS than on NMOS.展开更多
A study on the single event transient （SET） induced by a pulsed laser in a silicon-germanium （SiGe） heterojunction bipolar transistor （HBT） is presented in this work. The impacts of laser energy and collector lo...A study on the single event transient （SET） induced by a pulsed laser in a silicon-germanium （SiGe） heterojunction bipolar transistor （HBT） is presented in this work. The impacts of laser energy and collector load resistance on the SET are investigated in detail. The waveform, amplitude, and width of the SET pulse as well as collected charge are used to characterize the SET response. The experimental results are discussed in detail and it is demonstrated that the laser energy and load resistance significantly affect the SET in the SiGe HBT. Furthermore, the underlying physical mechanisms are analyzed and investigated, and a near-ideal exponential model is proposed for the first time to describe the discharge of laser-induced electrons via collector resistance to collector supply when both base-collector and collector-substrate junctions are reverse biased or weakly forward biased. Besides, it is found that an additional multi-path discharge would play an important role in the SET once the base-collector and collector-substrate junctions get strongly forward biased due to a strong transient step charge by the laser pulse.展开更多
This paper presents an investigation into the impact of proton-induced alteration of carrier lifetime on the singleevent transient(SET) caused by heavy ions in silicon–germanium heterojunction bipolar transistor(SiGe...This paper presents an investigation into the impact of proton-induced alteration of carrier lifetime on the singleevent transient(SET) caused by heavy ions in silicon–germanium heterojunction bipolar transistor(SiGe HBT).The ioninduced current transients and integrated charge collections under different proton fluences are obtained based on technology computer-aided design(TCAD) simulation.The results indicate that the impact of carrier lifetime alteration is determined by the dominating charge collection mechanism at the ion incident position and only the long-time diffusion process is affected.With a proton fluence of 5 × 1013 cm-2, almost no change is found in the transient feature, and the charge collection of events happened in the region enclosed by deep trench isolation(DTI), where prompt funneling collection is the dominating mechanism.Meanwhile, for the events happening outside DTI where diffusion dominates the collection process, the peak value and the duration of the ion-induced current transient both decrease with increasing proton fluence, leading to a great decrease in charge collection.展开更多
This paper investigates the temperature dependence of single-event transients（SETs） in 90-nm complementary metat-oxide semiconductor（CMOS） dual-well and triple-well negative metal-oxide semiconductor field-effect ...This paper investigates the temperature dependence of single-event transients（SETs） in 90-nm complementary metat-oxide semiconductor（CMOS） dual-well and triple-well negative metal-oxide semiconductor field-effect transistors（NMOSFETs）.Technology computer-aided design（TCAD） three-dimensional（3D） simulations show that the drain current pulse duration increases from 85 ps to 245 ps for triple-well but only increases from 65 ps to 98 ps for dual-well when the temperature increases from-55℃ to 125℃,which is closely correlated with the NMOSFET sources.This reveals that the pulse width increases with temperature in dual-well due to the weakening of the anti-amplification bipolar effect while increases with temperature in triple-well due to the enhancement of the bipolar amplification.展开更多
As technologies scale down in size, multiple-transistors being affected by a single ion has become a universal phenomenon, and some new effects are present in single event transients （SETs） due to the charge sharing...As technologies scale down in size, multiple-transistors being affected by a single ion has become a universal phenomenon, and some new effects are present in single event transients （SETs） due to the charge sharing collection of the adjacent multiple-transistors. In this paper, not only the off-state p-channel metal–oxide semiconductor field-effect transistor （PMOS FET）, but also the on-state PMOS is struck by a heavy-ion in the two-transistor inverter chain, due to the charge sharing collection and the electrical interaction. The SET induced by striking the off-state PMOS is efficiently mitigated by the pulse quenching effect, but the SET induced by striking the on-state PMOS becomes dominant. It is indicated in this study that in the advanced technologies, the SET will no longer just be induced by an ion striking the off-state transistor, and the SET sensitive region will no longer just surround the off-state transistor either, as it is in the older technologies. We also discuss this issue in a three-transistor inverter in depth, and the study illustrates that the three-transistor inverter is still a better replacement for spaceborne integrated circuit design in advanced technologies.展开更多
The single-event susceptibility of three silicon carbide(SiC)metal-oxide-semiconductor field-effect transistor(MOSFET)power devices structures(planar,trench and double trench)is researched by the technology computer-a...The single-event susceptibility of three silicon carbide(SiC)metal-oxide-semiconductor field-effect transistor(MOSFET)power devices structures(planar,trench and double trench)is researched by the technology computer-aided design(TCAD)simulation.Comparative analysis of the heavy-ion irradiation effects on three device structures reveals distinct susceptibility characteristics.The gate oxide region is identified as the most sensitive position in planar devices,while trench and doubletrench structures exhibit no localized sensitive regions.Furthermore,the single-event susceptibility demonstrates strong depth dependence across all three structures,with enhanced vulnerability observed at greater ion penetration depths.展开更多
Single-event transient pulse quenching （Quenching effect） is employed to effectively mitigate WSET （SET pulse width）. It en- hanced along with the increased charge sharing which is norm for future advanced technol...Single-event transient pulse quenching （Quenching effect） is employed to effectively mitigate WSET （SET pulse width）. It en- hanced along with the increased charge sharing which is norm for future advanced technologies. As technology scales, param- eter variation is another serious issue that significantly affects circuit＇s performance and single-event response. Monte Carlo simulations combined with TCAD （Technology Computer-Aided Design） simulations are conducted on a six-stage inverter chain to identify and quantify the impact of charge sharing and parameter variation on pulse quenching. Studies show that charge sharing induce a wider WSET spread range. The difference of WSET range between no quenching and quenching is smaller in NMOS （N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor） simulation than that in PMOS＇ （P-Channel Met- N-Oxide-Semiconductor Field-Effect Transistor）, so that from parameter variation view, quenching is beneficial in PMOS SET mitigation. The individual parameter analysis indicates that gate oxide thickness （TOXE） and channel length variation （XL） mostly affect SET response of combinational circuits. They bring 14.58% and 19.73% average WSET difference probabilities for no-quenching cases, and 105.56% and 123.32% for quenching cases.展开更多
A radiation-hardened-by-design （RHBD） technique for phase-locked loops （PLLs） has been developed for single-event transient （SET） mitigation. By presenting a novel SET-resistant complementary current limiter （...A radiation-hardened-by-design （RHBD） technique for phase-locked loops （PLLs） has been developed for single-event transient （SET） mitigation. By presenting a novel SET-resistant complementary current limiter （CCL） and implementing it between the charge pump （CP） and the loop filter （LPF）, the PLL＇s single-event susceptibility is significantly decreased in the presence of SETs in CPs, whereas it has little impact on the loop parameters in the absence of SETs in CPs. Transistor-level simulation results show that the CCL circuit can significantly reduce the voltage perturbation on the input of the voltage-controlled oscillator （VCO） by up to 93.1% and reduce the recovery time of the PLL by up to 79.0%. Moreover, the CCL circuit can also accelerate the PLL recovery procedure from loss of lock due to phase or frequency shift, as well as a single-event strike.展开更多
Single-event charge collection is controlled by drift, diffusion and the bipolar effect. Previous work has established that the bipolar effect is significant in the p-type metal-oxide-semiconductor field-effect transi...Single-event charge collection is controlled by drift, diffusion and the bipolar effect. Previous work has established that the bipolar effect is significant in the p-type metal-oxide-semiconductor field-effect transistor(PMOS) in 90 nm technology and above. However, the consequences of the bipolar effect on P-hit single-event transients have still not completely been characterized in 65 nm technology. In this paper, characterization of the consequences of the bipolar effect on P-hit single-event transients is performed by heavy ion experiments in both 65 nm twin-well and triple-well complementary metal-oxide-semiconductor(CMOS) technologies. Two inverter chains with clever layout structures are explored for the characterization. Ge(linear energy transfer(LET) = 37.4 Me V cm^2/mg) and Ti(LET = 22.2 Me V cm^2/mg) particles are also employed. The experimental results show that with Ge(Ti) exposure, the average pulse reduction is 49 ps(45 ps) in triple-well CMOS technology and 42 ps(32 ps) in twin-well CMOS technology when the bipolar effect is efficiently mitigated. This characterization will provide an important reference for radiation hardening integrated circuit design.展开更多
This study presents a real-time tracking algorithm derived from the retina algorithm,designed for the rapid,real-time tracking of straight-line particle trajectories.These trajectories are detected by pixel detectors ...This study presents a real-time tracking algorithm derived from the retina algorithm,designed for the rapid,real-time tracking of straight-line particle trajectories.These trajectories are detected by pixel detectors to localize single-event effects in two-dimensional space.Initially,we developed a retina algorithm to track the trajectory of a single heavy ion and achieved a positional accuracy of 40μm.This was accomplished by analyzing trajectory samples from the simulations using a pixel sensor with a 72×72 pixel array and an 83μm pixel pitch.Subsequently,we refined this approach to create an iterative retina algorithm for tracking multiple heavy-ion trajectories in single events.This iterative version demonstrated a tracking efficiency of over 97%,with a positional resolution comparable to that of single-track events.Furthermore,it exhibits significant parallelism,requires fewer resources,and is ideally suited for implementation in field-programmable gate arrays on board-level systems,facilitating real-time online trajectory tracking.展开更多
This work proposes and fabricates the 4H-SiC power MOSFET with top oxide and double P-well(TODP-MOSFET)to enhance the single-event radiation tolerance of the gate oxide.Simulation results suggest that the proposed TOD...This work proposes and fabricates the 4H-SiC power MOSFET with top oxide and double P-well(TODP-MOSFET)to enhance the single-event radiation tolerance of the gate oxide.Simulation results suggest that the proposed TODP structure reduces the peak electric field within the oxide and minimizes the sensitive region by more than 70%compared to C-MOSFETs.Experimental results show that the gate degradation voltage of the TODP-MOSFET is higher than that of the C-MOSFET,and the gate leakage current is reduced by 95%compared to the C-MOSFET under heavy-ion irradiation with a linear energy transfer(LET)value exceeding 75 MeV·cm^(2)/mg.展开更多
This paper explores the impact of back-gate bias (V_(soi)) and supply voltage (V_(DD)) on the single-event upset (SEU) cross section of 0.18μm configurable silicon-on-insulator static random-access memory (SRAM) unde...This paper explores the impact of back-gate bias (V_(soi)) and supply voltage (V_(DD)) on the single-event upset (SEU) cross section of 0.18μm configurable silicon-on-insulator static random-access memory (SRAM) under high linear energy transfer heavyion experimentation.The experimental findings demonstrate that applying a negative back-gate bias to NMOS and a positive back-gate bias to PMOS enhances the SEU resistance of SRAM.Specifically,as the back-gate bias for N-type transistors(V_(nsoi)) decreases from 0 to-10 V,the SEU cross section decreases by 93.23%,whereas an increase in the back-gate bias for P-type transistors (V_(psoi)) from 0 to 10 V correlates with an 83.7%reduction in SEU cross section.Furthermore,a significant increase in the SEU cross section was observed with increase in supply voltage,as evidenced by a 159%surge at V_(DD)=1.98 V compared with the nominal voltage of 1.8 V.To explore the physical mechanisms underlying these experimental data,we analyzed the dependence of the critical charge of the circuit and the collected charge on the bias voltage by simulating SEUs using technology computer-aided design.展开更多
It has been shown that charge pumps （CPs） dominate single-event transient （SET） responses of phase- locked loops （PLLs）. Using a pulse to represent a single event hit on CPs, the SET analysis model is establishe...It has been shown that charge pumps （CPs） dominate single-event transient （SET） responses of phase- locked loops （PLLs）. Using a pulse to represent a single event hit on CPs, the SET analysis model is established and the characteristics of SET generation and propagation in PLLs are revealed. An analysis of single event transients in PLLs demonstrates that the settling time of the voltage-controlled oscillators （VCOs） control voltage after a single event strike is strongly dependent on the peak control voltage deviation, the SET pulse width, and the settling time constant. And the peak control voltage disturbance decreases with the SET strength or the filter resistance. Further- more, the analysis in the proposed PLL model is confirmed by simulation results using MATLAB and HSPICE, respectively.展开更多
The single event transient(SET)effect in nanotube tunneling field-effect transistor with bias-induced electron–hole bilayer(EHBNT-TFET)is investigated by 3-D TCAD simulation for the first time.The effects of linear e...The single event transient(SET)effect in nanotube tunneling field-effect transistor with bias-induced electron–hole bilayer(EHBNT-TFET)is investigated by 3-D TCAD simulation for the first time.The effects of linear energy transfer(LET),characteristic radius,strike angle,electrode bias and hit location on SET response are evaluated in detail.The simulation results show that the peak value of transient drain current is up to 0.08 m A for heavy ion irradiation with characteristic radius of 50 nm and LET of 10 Me V·cm^(2)/mg,which is much higher than the on-state current of EHBNTTFET.The SET response of EHBNT-TFET presents an obvious dependence on LET,strike angle,drain bias and hit location.As LET increases from 2 Me V·cm^(2)/mg to 10 Me V·cm^(2)/mg,the peak drain current increases monotonically from 0.015 mA to 0.08 mA.The strike angle has an greater impact on peak drain current especially for the smaller characteristic radius.The peak drain current and collected charge increase by 0.014 mA and 0.06 fC,respectively,as the drain bias increases from 0.1 V to 0.9 V.Whether from the horizontal or the vertical direction,the most sensitive hit location is related to wt.The underlying physical mechanism is explored and discussed.展开更多
Recent years,the hardening of combinational circuits is becoming a common concern.Unlike the transistor-level hardening technique,the cell-level hardening technique,a divide and conquer strategy,can substantially make...Recent years,the hardening of combinational circuits is becoming a common concern.Unlike the transistor-level hardening technique,the cell-level hardening technique,a divide and conquer strategy,can substantially make use of some typical character in the cell-circuit module to mitigate single event transient(SET)sensitivity.The mirror image(MI)technique proposed in this paper can adequately enhance the charge sharing in those cell-circuits with stage-by-stage inverter-like structure.3D TCAD mixed-mode simulation have been performed in 65 nm twinwell bulk CMOS process,the results indicate that the MI technique can almost reduce the SET pulse width from the anterior-stage PMOS over 25%,and can mitigate the SET pulse width from the posterior-stage PMOS about 10%.The MI technique,a represent of the cell-level technique,may be the future of the hardening of combinational circuits.展开更多
基金supported by Natural Science Foundation of China(Nos.62174180 and 62304258)National Key R&D Program of China(No.2023YFA1609000)。
文摘This paper quantitatively discusses the influence of well contact on single-event transient(SET)in sub-20 nm FinFET by two-photon absorption(TPA)pulse laser.Two groups of inverter chains were designed to investigate the impact of well contact distance on the FinFET process.The experimental results show that the SET pulse width has a bimodal symmetric distribution,which is different from that of a bulk planar CMOS device.To investigate the detailed mechanism of the phenomenon,a high-precision FinFET TCAD model was established,in which both Id-Vd and Id-Vg errors were less than 10%compared to the SPICE model provided by the commercial process.TCAD simulation under heavy ion injection showed the mechanism of the abnormal phenomenon,where the well contact plays a major role in charge collection at the near-well contact distance,while the source plays a major role at the far distance.This phenomenon is completely different from that of planar CMOS devices.This indicates that the SET mechanism becomes more complicated during the FinFET process.Therefore,more effective SET hardening methods should be investigated for FinFET.
基金the National Natural Science Foundation of China(Grant Nos.61704127 and 11775167)。
文摘We experimentally demonstrate that the dominant mechanism of single-event transients in silicon-germanium heterojunction bipolar transistors(SiGe HBTs)can change with decreasing temperature from+20℃to-180℃.This is accomplished by using a new well-designed cryogenic experimental system suitable for a pulsed-laser platform.Firstly,when the temperature drops from+20℃to-140℃,the increased carrier mobility drives a slight increase in transient amplitude.However,as the temperature decreases further below-140℃,the carrier freeze-out brings about an inflection point,which means the transient amplitude will decrease at cryogenic temperatures.To better understand this result,we analytically calculate the ionization rates of various dopants at different temperatures based on Altermatt's new incomplete ionization model.The parasitic resistivities with temperature on the charge-collection pathway are extracted by a two-dimensional(2D)TCAD process simulation.In addition,we investigate the impact of temperature on the novel electron-injection process from emitter to base under different bias conditions.The increase of the emitter-base junction's barrier height at low temperatures could suppress this electron-injection phenomenon.We have also optimized the built-in voltage equations of a high current compact model(HICUM)by introducing the impact of incomplete ionization.The present results and methods could provide a new reference for effective evaluation of single-event effects in bipolar transistors and circuits at cryogenic temperatures,and could provide a new evidence of the potential of SiGe technology in applications in extreme cryogenic environments.
基金Project supported by the National Natural Science Foundation of China(Grant No.61376109)the Opening Project of National Key Laboratory of Science and Technology on Reliability Physics and Application Technology of Electrical Component,China(Grant No.ZHD201202)
文摘As integrated circuits scale down in size, a single high-energy ion strike often affects multiple adjacent logic nodes.The so-called single-event transient（SET） pulse quenching induced by single-event charge sharing collection has been widely studied. In this paper, SET pulse quenching enhancement is found in dummy gate isolated adjacent logic nodes compared with that isolated by the common shallow trench isolation（STI）. The physical mechanism is studied in depth and this isolation technique is explored for SET mitigation in combinational standard cells. Three-dimensional（3D） technology computer-aided design simulation（TCAD） results show that this technique can achieve efficient SET mitigation.
基金Project supported by Funds of Key Laboratory,China(Grant No.y7ys011001)Youth Innovation Promotion Association,Chinese Academy of Sciences(Grant No.y5yq01r002)
文摘In this study, we investigate the single-event transient（SET） characteristics of a partially depleted silicon-on-insulator（PDSOI） metal-oxide-semiconductor（MOS） device induced by a pulsed laser.We measure and analyze the drain transient current at the wafer level. The results indicate that the body-drain junction and its vicinity are more SET sensitive than the other regions in PD-SOI devices.We use ISE 3D simulation tools to analyze the SET response when different regions of the device are hit. Then, we discuss in detail the characteristics of transient currents and the electrostatic potential distribution change in devices after irradiation. Finally, we analyze the parasitic bipolar junction transistor（p-BJT） effect by performing both a laser test and simulations.
基金supported by the National Natural Science Foundation of China(Nos.61434007 and 61376109)
文摘Based on 3 D-TCAD simulations, single-event transient(SET) effects and charge collection mechanisms in fully depleted silicon-on-insulator(FDSOI) transistors are investigated. This work presents a comparison between28-nm technology and 0.2-lm technology to analyze the impact of strike location on SET sensitivity in FDSOI devices. Simulation results show that the most SET-sensitive region in FDSOI transistors is the drain region near the gate. An in-depth analysis shows that the bipolar amplification effect in FDSOI devices is dependent on the strike locations. In addition, when the drain contact is moved toward the drain direction, the most sensitive region drifts toward the drain and collects more charge. This provides theoretical guidance for SET hardening.
基金Project supported by the State Key Program of the National Natural Science Foundation of China (Grant No. 60836004)the National Natural Science Foundation of China (Grant Nos. 61076025 and 61006070)
文摘Variation of substrate background doping will affect the charge collection of active and passive MOSFETs in complementary metal-oxide semiconductor （CMOS） technologies, which are significant for charge sharing, thus affecting the propagated single event transient pulsewidths in circuits. The trends of charge collected by the drain of a positive channel metal-oxide semiconductor （PMOS） and an N metal-oxide semiconductor （NMOS） are opposite as the substrate doping increases. The PMOS source will inject carriers after strike and the amount of charge injected will irlcrease as the substrate doping increases, whereas the source of the NMOS will mainly collect carriers and the source of the NMOS can also inject electrons when the substrate doping is light enough. Additionally, it indicates that substrate doping mainly affects the bipolar amplification component of a single-event transient current, and has little effect on the drift and diffusion. The change in substrate doping has a much greater effect on PMOS than on NMOS.
基金Project supported by the National Natural Science Foundation of China (Grant No. 60976013)
文摘A study on the single event transient （SET） induced by a pulsed laser in a silicon-germanium （SiGe） heterojunction bipolar transistor （HBT） is presented in this work. The impacts of laser energy and collector load resistance on the SET are investigated in detail. The waveform, amplitude, and width of the SET pulse as well as collected charge are used to characterize the SET response. The experimental results are discussed in detail and it is demonstrated that the laser energy and load resistance significantly affect the SET in the SiGe HBT. Furthermore, the underlying physical mechanisms are analyzed and investigated, and a near-ideal exponential model is proposed for the first time to describe the discharge of laser-induced electrons via collector resistance to collector supply when both base-collector and collector-substrate junctions are reverse biased or weakly forward biased. Besides, it is found that an additional multi-path discharge would play an important role in the SET once the base-collector and collector-substrate junctions get strongly forward biased due to a strong transient step charge by the laser pulse.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.11775167,61574171,11575138,and 11835006)
文摘This paper presents an investigation into the impact of proton-induced alteration of carrier lifetime on the singleevent transient(SET) caused by heavy ions in silicon–germanium heterojunction bipolar transistor(SiGe HBT).The ioninduced current transients and integrated charge collections under different proton fluences are obtained based on technology computer-aided design(TCAD) simulation.The results indicate that the impact of carrier lifetime alteration is determined by the dominating charge collection mechanism at the ion incident position and only the long-time diffusion process is affected.With a proton fluence of 5 × 1013 cm-2, almost no change is found in the transient feature, and the charge collection of events happened in the region enclosed by deep trench isolation(DTI), where prompt funneling collection is the dominating mechanism.Meanwhile, for the events happening outside DTI where diffusion dominates the collection process, the peak value and the duration of the ion-induced current transient both decrease with increasing proton fluence, leading to a great decrease in charge collection.
基金Project supported by the State Key Program of the National Natural Science Foundation of China (Grant No. 60836004)Innovation Foundation for Postgraduate of Hunan Province,China (Grant No. CX2011B026)
文摘This paper investigates the temperature dependence of single-event transients（SETs） in 90-nm complementary metat-oxide semiconductor（CMOS） dual-well and triple-well negative metal-oxide semiconductor field-effect transistors（NMOSFETs）.Technology computer-aided design（TCAD） three-dimensional（3D） simulations show that the drain current pulse duration increases from 85 ps to 245 ps for triple-well but only increases from 65 ps to 98 ps for dual-well when the temperature increases from-55℃ to 125℃,which is closely correlated with the NMOSFET sources.This reveals that the pulse width increases with temperature in dual-well due to the weakening of the anti-amplification bipolar effect while increases with temperature in triple-well due to the enhancement of the bipolar amplification.
基金Project supported by the Key Program of the National Natural Science Foundation of China (Grant No. 61133007)the National Natural Science Foundation of China (Grant Nos. 61006070 and 61076025)
文摘As technologies scale down in size, multiple-transistors being affected by a single ion has become a universal phenomenon, and some new effects are present in single event transients （SETs） due to the charge sharing collection of the adjacent multiple-transistors. In this paper, not only the off-state p-channel metal–oxide semiconductor field-effect transistor （PMOS FET）, but also the on-state PMOS is struck by a heavy-ion in the two-transistor inverter chain, due to the charge sharing collection and the electrical interaction. The SET induced by striking the off-state PMOS is efficiently mitigated by the pulse quenching effect, but the SET induced by striking the on-state PMOS becomes dominant. It is indicated in this study that in the advanced technologies, the SET will no longer just be induced by an ion striking the off-state transistor, and the SET sensitive region will no longer just surround the off-state transistor either, as it is in the older technologies. We also discuss this issue in a three-transistor inverter in depth, and the study illustrates that the three-transistor inverter is still a better replacement for spaceborne integrated circuit design in advanced technologies.
基金National Key Research and Development Program of China(2023YFA1609000)National Natural Science Foundation of China(62474190,U22B2043,U2267210)。
文摘The single-event susceptibility of three silicon carbide(SiC)metal-oxide-semiconductor field-effect transistor(MOSFET)power devices structures(planar,trench and double trench)is researched by the technology computer-aided design(TCAD)simulation.Comparative analysis of the heavy-ion irradiation effects on three device structures reveals distinct susceptibility characteristics.The gate oxide region is identified as the most sensitive position in planar devices,while trench and doubletrench structures exhibit no localized sensitive regions.Furthermore,the single-event susceptibility demonstrates strong depth dependence across all three structures,with enhanced vulnerability observed at greater ion penetration depths.
基金supported by the Harbin Science and Innovation Research.(Grant No.2012RFXXG042)
文摘Single-event transient pulse quenching （Quenching effect） is employed to effectively mitigate WSET （SET pulse width）. It en- hanced along with the increased charge sharing which is norm for future advanced technologies. As technology scales, param- eter variation is another serious issue that significantly affects circuit＇s performance and single-event response. Monte Carlo simulations combined with TCAD （Technology Computer-Aided Design） simulations are conducted on a six-stage inverter chain to identify and quantify the impact of charge sharing and parameter variation on pulse quenching. Studies show that charge sharing induce a wider WSET spread range. The difference of WSET range between no quenching and quenching is smaller in NMOS （N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor） simulation than that in PMOS＇ （P-Channel Met- N-Oxide-Semiconductor Field-Effect Transistor）, so that from parameter variation view, quenching is beneficial in PMOS SET mitigation. The individual parameter analysis indicates that gate oxide thickness （TOXE） and channel length variation （XL） mostly affect SET response of combinational circuits. They bring 14.58% and 19.73% average WSET difference probabilities for no-quenching cases, and 105.56% and 123.32% for quenching cases.
基金supported by the National Natural Science Foundation of China(Nos.60836004,60676010)the PhD Program of Ministry of Education of China(No.20079998015)the Program for Changjiang Scholars and Innovative Research Team in University of China
文摘A radiation-hardened-by-design （RHBD） technique for phase-locked loops （PLLs） has been developed for single-event transient （SET） mitigation. By presenting a novel SET-resistant complementary current limiter （CCL） and implementing it between the charge pump （CP） and the loop filter （LPF）, the PLL＇s single-event susceptibility is significantly decreased in the presence of SETs in CPs, whereas it has little impact on the loop parameters in the absence of SETs in CPs. Transistor-level simulation results show that the CCL circuit can significantly reduce the voltage perturbation on the input of the voltage-controlled oscillator （VCO） by up to 93.1% and reduce the recovery time of the PLL by up to 79.0%. Moreover, the CCL circuit can also accelerate the PLL recovery procedure from loss of lock due to phase or frequency shift, as well as a single-event strike.
基金supported by the National Natural Science Foundation of China(Grant No.61504169)the Preliminary Research Program of National University of Defense Technology of China(Grant No.0100066314001)
文摘Single-event charge collection is controlled by drift, diffusion and the bipolar effect. Previous work has established that the bipolar effect is significant in the p-type metal-oxide-semiconductor field-effect transistor(PMOS) in 90 nm technology and above. However, the consequences of the bipolar effect on P-hit single-event transients have still not completely been characterized in 65 nm technology. In this paper, characterization of the consequences of the bipolar effect on P-hit single-event transients is performed by heavy ion experiments in both 65 nm twin-well and triple-well complementary metal-oxide-semiconductor(CMOS) technologies. Two inverter chains with clever layout structures are explored for the characterization. Ge(linear energy transfer(LET) = 37.4 Me V cm^2/mg) and Ti(LET = 22.2 Me V cm^2/mg) particles are also employed. The experimental results show that with Ge(Ti) exposure, the average pulse reduction is 49 ps(45 ps) in triple-well CMOS technology and 42 ps(32 ps) in twin-well CMOS technology when the bipolar effect is efficiently mitigated. This characterization will provide an important reference for radiation hardening integrated circuit design.
基金supported by the National Natural Science Foundation of China(No.12205224)the Research Foundation of Education Bureau of Hubei Province China(No.Q20221703)+1 种基金the National Natural Science Foundation of China(Nos.12035006,U2032140)the National Key Research and Development Program of China(No.2020YFE0202000)。
文摘This study presents a real-time tracking algorithm derived from the retina algorithm,designed for the rapid,real-time tracking of straight-line particle trajectories.These trajectories are detected by pixel detectors to localize single-event effects in two-dimensional space.Initially,we developed a retina algorithm to track the trajectory of a single heavy ion and achieved a positional accuracy of 40μm.This was accomplished by analyzing trajectory samples from the simulations using a pixel sensor with a 72×72 pixel array and an 83μm pixel pitch.Subsequently,we refined this approach to create an iterative retina algorithm for tracking multiple heavy-ion trajectories in single events.This iterative version demonstrated a tracking efficiency of over 97%,with a positional resolution comparable to that of single-track events.Furthermore,it exhibits significant parallelism,requires fewer resources,and is ideally suited for implementation in field-programmable gate arrays on board-level systems,facilitating real-time online trajectory tracking.
基金supported by the Joint Funds of the National Natural Science Foundation of China(Grant No.U2341220)the Hefei Comprehensive National Science Center。
文摘This work proposes and fabricates the 4H-SiC power MOSFET with top oxide and double P-well(TODP-MOSFET)to enhance the single-event radiation tolerance of the gate oxide.Simulation results suggest that the proposed TODP structure reduces the peak electric field within the oxide and minimizes the sensitive region by more than 70%compared to C-MOSFETs.Experimental results show that the gate degradation voltage of the TODP-MOSFET is higher than that of the C-MOSFET,and the gate leakage current is reduced by 95%compared to the C-MOSFET under heavy-ion irradiation with a linear energy transfer(LET)value exceeding 75 MeV·cm^(2)/mg.
基金supported by the National Key Laboratory of Materials Behavior and Evaluation Technology in Space Environment(No.6142910220208)National Natural Science Foundation of China(Nos.12105341 and 12035019)the opening fund of Key Laboratory of Silicon Device and Technology,Chinese Academy of Sciences(No.KLSDTJJ2022-3).
文摘This paper explores the impact of back-gate bias (V_(soi)) and supply voltage (V_(DD)) on the single-event upset (SEU) cross section of 0.18μm configurable silicon-on-insulator static random-access memory (SRAM) under high linear energy transfer heavyion experimentation.The experimental findings demonstrate that applying a negative back-gate bias to NMOS and a positive back-gate bias to PMOS enhances the SEU resistance of SRAM.Specifically,as the back-gate bias for N-type transistors(V_(nsoi)) decreases from 0 to-10 V,the SEU cross section decreases by 93.23%,whereas an increase in the back-gate bias for P-type transistors (V_(psoi)) from 0 to 10 V correlates with an 83.7%reduction in SEU cross section.Furthermore,a significant increase in the SEU cross section was observed with increase in supply voltage,as evidenced by a 159%surge at V_(DD)=1.98 V compared with the nominal voltage of 1.8 V.To explore the physical mechanisms underlying these experimental data,we analyzed the dependence of the critical charge of the circuit and the collected charge on the bias voltage by simulating SEUs using technology computer-aided design.
基金supported by the National Natural Science Foundation of China(Nos.60836004,60676010)the PhD Program Foundation of the Ministry of Education of China(No.20079998015)
文摘It has been shown that charge pumps （CPs） dominate single-event transient （SET） responses of phase- locked loops （PLLs）. Using a pulse to represent a single event hit on CPs, the SET analysis model is established and the characteristics of SET generation and propagation in PLLs are revealed. An analysis of single event transients in PLLs demonstrates that the settling time of the voltage-controlled oscillators （VCOs） control voltage after a single event strike is strongly dependent on the peak control voltage deviation, the SET pulse width, and the settling time constant. And the peak control voltage disturbance decreases with the SET strength or the filter resistance. Further- more, the analysis in the proposed PLL model is confirmed by simulation results using MATLAB and HSPICE, respectively.
基金Project supported in part by the National Natural Science Foundation of China(Grant No.61974056)the Natural Science Foundation of Shanghai(Grant No.19ZR1471300)+1 种基金Shanghai Science and Technology Innovation Action Plan(Grant No.19511131900)Shanghai Science and Technology Explorer Plan(Grant No.21TS1401700)。
文摘The single event transient(SET)effect in nanotube tunneling field-effect transistor with bias-induced electron–hole bilayer(EHBNT-TFET)is investigated by 3-D TCAD simulation for the first time.The effects of linear energy transfer(LET),characteristic radius,strike angle,electrode bias and hit location on SET response are evaluated in detail.The simulation results show that the peak value of transient drain current is up to 0.08 m A for heavy ion irradiation with characteristic radius of 50 nm and LET of 10 Me V·cm^(2)/mg,which is much higher than the on-state current of EHBNTTFET.The SET response of EHBNT-TFET presents an obvious dependence on LET,strike angle,drain bias and hit location.As LET increases from 2 Me V·cm^(2)/mg to 10 Me V·cm^(2)/mg,the peak drain current increases monotonically from 0.015 mA to 0.08 mA.The strike angle has an greater impact on peak drain current especially for the smaller characteristic radius.The peak drain current and collected charge increase by 0.014 mA and 0.06 fC,respectively,as the drain bias increases from 0.1 V to 0.9 V.Whether from the horizontal or the vertical direction,the most sensitive hit location is related to wt.The underlying physical mechanism is explored and discussed.
基金supported by the National Natural Science Foundation of China (61376109)
文摘Recent years,the hardening of combinational circuits is becoming a common concern.Unlike the transistor-level hardening technique,the cell-level hardening technique,a divide and conquer strategy,can substantially make use of some typical character in the cell-circuit module to mitigate single event transient(SET)sensitivity.The mirror image(MI)technique proposed in this paper can adequately enhance the charge sharing in those cell-circuits with stage-by-stage inverter-like structure.3D TCAD mixed-mode simulation have been performed in 65 nm twinwell bulk CMOS process,the results indicate that the MI technique can almost reduce the SET pulse width from the anterior-stage PMOS over 25%,and can mitigate the SET pulse width from the posterior-stage PMOS about 10%.The MI technique,a represent of the cell-level technique,may be the future of the hardening of combinational circuits.
