The tokamak HT-7U project has been funded as a Chinese national project since 1998. The main object of the project is to build a nuclear fusion experimental device with divertor configuration, which is designed by the...The tokamak HT-7U project has been funded as a Chinese national project since 1998. The main object of the project is to build a nuclear fusion experimental device with divertor configuration, which is designed by the Institute of Plasma Physics, the Chinese Academy of Sciences (ASIPP). It is a full superconducting device, consisting of superconducting toroidal field (TF) coils and superconducting poloidal field (PF) coil. During the operation of the device, the operational parameter of device should be checked by technical diagnosis. This paper describes the design of circuit for checldng short between every two parts of the HT7U device. The main contents of design include circuit of data acquisition and data processing of computer.展开更多
A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is...A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise. The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly,an out-band phase noise of -139dBc/Hz at 3MHz offset frequency, and a fractional spur of less than - 60dBc. The chip area is 1.5mm × 1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage.展开更多
ZnO whiskers observation on the surface of SnZn/Cu solder joints in concentrator silicon solar cells solder layer is reported. In the experiment,SnZn/Cu samples are left in laboratory after reflow soldering for two ye...ZnO whiskers observation on the surface of SnZn/Cu solder joints in concentrator silicon solar cells solder layer is reported. In the experiment,SnZn/Cu samples are left in laboratory after reflow soldering for two years before an examination by SEM,then ZnO whiskers can be observed obviously,which grows out from the rich-Zn phase of the samples and causes electrical short circuit in the electronics appliances,which demonstrates that the SnZn solder shows a risk for the short circuiting failure of an electronic device. Moreover,the growth mechanism of ZnO whiskers is researched based on cracked oxide theory,which provides the reference support for SnZn solders application.展开更多
Digital calibration and control techniques for narrow band integrated low-IF receivers with on-chip frequency synthesizer are presented.The calibration and control system,which is adopted to ensure an achievable signa...Digital calibration and control techniques for narrow band integrated low-IF receivers with on-chip frequency synthesizer are presented.The calibration and control system,which is adopted to ensure an achievable signal-to-noise ratio and bit error rate,consists of a digitally controlled,high resolution dB-linear automatic gain control（AGC）,an inphase（I） and quadrature（Q） gain and phase mismatch calibration,and an automatic frequency calibration（AFC） of a wideband voltage-controlled oscillator in a PLL based frequency synthesizer.The calibration system has a low design complexity with little power and small die area.Simulation results show that the calibration system can enlarge the dynamic range to 72 dB and minimize the phase and amplitude imbalance between I and Q to 0.08° and 0.024 dB,respectively,which means the image rejection ratio is better than 60 dB.In addition,the calibration time of the AFC is 1.12 μs only with a reference clock of 100 MHz.展开更多
A receiver for SRDs implemented by the 0.35μm CMOS process is presented. The receiver, together with the ADC, power amplifier （PA）, frequency synthesizer and digital baseband has been integrated into a single chip ...A receiver for SRDs implemented by the 0.35μm CMOS process is presented. The receiver, together with the ADC, power amplifier （PA）, frequency synthesizer and digital baseband has been integrated into a single chip solution. Low cost and low power requirements are met by optimizing the receiver architecture and circuit topology. A simple mixed-signal mode I/Q imbalance calibration circuit is proposed to enhance the IRR （image rejection ratio） so as to raise the BER. From a single 3 V power supply, the receiver consumes 5.9 mA. The measurement result shows that the receiver achieves reference sensitivity of-60 dBm and a control gain of 60 dB. The S11 reaches -20 dB at 433 MHz and -10 dB at 868 MHz without off-chip impedance match network. The die area is only 2 mm^2 including the bias circuit.展开更多
This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier （LNA）, current-reuse V-I converter, active double balanced mixer and transimpedance amplifier for short range device...This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier （LNA）, current-reuse V-I converter, active double balanced mixer and transimpedance amplifier for short range device （SRD） applications. With the proposed current-reuse LNA, the DC consumption of the front-end reduces considerably while maintaining sufficient performance needed by SRD devices. The RF front-end was fabricated in 0.18μm RFCMOS process and occupies a silicon area of just 0.11 mm^2. Operating in 433 MHz band, the measurement results show the RF front-end achieves a conversion gain of 29.7 dB, a double side band noise figure of 9.7 dB, an input referenced third intercept point of -24.9 dBm with only 1.44 mA power consumption from 1.8 V supply. Compared to other reported front-ends, it has an advantage in power consumption.展开更多
文摘The tokamak HT-7U project has been funded as a Chinese national project since 1998. The main object of the project is to build a nuclear fusion experimental device with divertor configuration, which is designed by the Institute of Plasma Physics, the Chinese Academy of Sciences (ASIPP). It is a full superconducting device, consisting of superconducting toroidal field (TF) coils and superconducting poloidal field (PF) coil. During the operation of the device, the operational parameter of device should be checked by technical diagnosis. This paper describes the design of circuit for checldng short between every two parts of the HT7U device. The main contents of design include circuit of data acquisition and data processing of computer.
文摘A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise. The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly,an out-band phase noise of -139dBc/Hz at 3MHz offset frequency, and a fractional spur of less than - 60dBc. The chip area is 1.5mm × 1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage.
基金Supported by the National Natural Science Foundation of China(No.51475220)State Foundation of Laboratory of Advanced Brazing Filler Metals&Technology(Zhengzhou Research Institute of Mechanical Engineering)(No.SKLABFMT-2015-03)High Level Talent Plan of Jiangsu Normal University(No.YQ2015002)
文摘ZnO whiskers observation on the surface of SnZn/Cu solder joints in concentrator silicon solar cells solder layer is reported. In the experiment,SnZn/Cu samples are left in laboratory after reflow soldering for two years before an examination by SEM,then ZnO whiskers can be observed obviously,which grows out from the rich-Zn phase of the samples and causes electrical short circuit in the electronics appliances,which demonstrates that the SnZn solder shows a risk for the short circuiting failure of an electronic device. Moreover,the growth mechanism of ZnO whiskers is researched based on cracked oxide theory,which provides the reference support for SnZn solders application.
文摘Digital calibration and control techniques for narrow band integrated low-IF receivers with on-chip frequency synthesizer are presented.The calibration and control system,which is adopted to ensure an achievable signal-to-noise ratio and bit error rate,consists of a digitally controlled,high resolution dB-linear automatic gain control（AGC）,an inphase（I） and quadrature（Q） gain and phase mismatch calibration,and an automatic frequency calibration（AFC） of a wideband voltage-controlled oscillator in a PLL based frequency synthesizer.The calibration system has a low design complexity with little power and small die area.Simulation results show that the calibration system can enlarge the dynamic range to 72 dB and minimize the phase and amplitude imbalance between I and Q to 0.08° and 0.024 dB,respectively,which means the image rejection ratio is better than 60 dB.In addition,the calibration time of the AFC is 1.12 μs only with a reference clock of 100 MHz.
文摘A receiver for SRDs implemented by the 0.35μm CMOS process is presented. The receiver, together with the ADC, power amplifier （PA）, frequency synthesizer and digital baseband has been integrated into a single chip solution. Low cost and low power requirements are met by optimizing the receiver architecture and circuit topology. A simple mixed-signal mode I/Q imbalance calibration circuit is proposed to enhance the IRR （image rejection ratio） so as to raise the BER. From a single 3 V power supply, the receiver consumes 5.9 mA. The measurement result shows that the receiver achieves reference sensitivity of-60 dBm and a control gain of 60 dB. The S11 reaches -20 dB at 433 MHz and -10 dB at 868 MHz without off-chip impedance match network. The die area is only 2 mm^2 including the bias circuit.
文摘This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier （LNA）, current-reuse V-I converter, active double balanced mixer and transimpedance amplifier for short range device （SRD） applications. With the proposed current-reuse LNA, the DC consumption of the front-end reduces considerably while maintaining sufficient performance needed by SRD devices. The RF front-end was fabricated in 0.18μm RFCMOS process and occupies a silicon area of just 0.11 mm^2. Operating in 433 MHz band, the measurement results show the RF front-end achieves a conversion gain of 29.7 dB, a double side band noise figure of 9.7 dB, an input referenced third intercept point of -24.9 dBm with only 1.44 mA power consumption from 1.8 V supply. Compared to other reported front-ends, it has an advantage in power consumption.
