A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is presented.For comparison,a conventional parallel acce...A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is presented.For comparison,a conventional parallel access cache with the same storage and organization is also designed and simulated using the same technology.Simulation results indicate that by using sequential access,power reduction of 26% on a cache hit and 35% on a cache miss is achieved.High-speed approaches including modified current-mode sense amplifier and split dynamic tag comparators are adopted to achieve fast data access.Simulation results indicate that a typical clock to data access of 2.7ns is achieved...展开更多
Trichloroethylene （TCE） is a major pollutant that affects both occupational and general environments. The liver is an important target organ of TCEE. Substantial efforts and remarkable progress into understanding TC...Trichloroethylene （TCE） is a major pollutant that affects both occupational and general environments. The liver is an important target organ of TCEE. Substantial efforts and remarkable progress into understanding TCE cytotoxicity have been made in cultured liver cells. However, the molecular mechanisms by which TCE induces hepatotoxicity are not well understood. SET （also known as protein phosphatase 2A inhibitor, 12PP2A, or template-activating factor-I, TAF-D is a nuclear protein that regulates histone modification, gene transcription, DNA replication, nucleosome assembly,展开更多
Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory speed.This paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual...Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory speed.This paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual port content addressable memory(DPCAM).In addition,it proposes a new replacement algorithm based on hardware which is called a near-far access replacement algorithm(NFRA)to reduce the cost overhead of the cache controller and improve the cache access latency.The experimental results indicated that the latency for write and read operations are significantly less in comparison with a set-associative cache memory.Moreover,it was shown that a latency of a read operation is nearly constant regardless of the size of DPCAM.However,an estimation of the power dissipation showed that DPCAM consumes about 7%greater than a set-associative cache memory of the same size.These results encourage for embedding DPCAM within the multicore processors as a small shared cache memory.展开更多
Die-stacked dynamic random access memory(DRAM)caches are increasingly advocated to bridge the performance gap between the on-chip cache and the main memory.To fully realize their potential,it is essential to improve D...Die-stacked dynamic random access memory(DRAM)caches are increasingly advocated to bridge the performance gap between the on-chip cache and the main memory.To fully realize their potential,it is essential to improve DRAM cache hit rate and lower its cache hit latency.In order to take advantage of the high hit-rate of set-association and the low hit latency of direct-mapping at the same time,we propose a partial direct-mapped die-stacked DRAM cache called P3DC.This design is motivated by a key observation,i.e.,applying a unified mapping policy to different types of blocks cannot achieve a high cache hit rate and low hit latency simultaneously.To address this problem,P3DC classifies data blocks into leading blocks and following blocks,and places them at static positions and dynamic positions,respectively,in a unified set-associative structure.We also propose a replacement policy to balance the miss penalty and the temporal locality of different blocks.In addition,P3DC provides a policy to mitigate cache thrashing due to block type variations.Experimental results demonstrate that P3DC can reduce the cache hit latency by 20.5%while achieving a similar cache hit rate compared with typical set-associative caches.P3DC improves the instructions per cycle(IPC)by up to 66%(12%on average)compared with the state-of-the-art direct-mapped cache—BEAR,and by up to 19%(6%on average)compared with the tag-data decoupled set-associative cache—DEC-A8.展开更多
文摘A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is presented.For comparison,a conventional parallel access cache with the same storage and organization is also designed and simulated using the same technology.Simulation results indicate that by using sequential access,power reduction of 26% on a cache hit and 35% on a cache miss is achieved.High-speed approaches including modified current-mode sense amplifier and split dynamic tag comparators are adopted to achieve fast data access.Simulation results indicate that a typical clock to data access of 2.7ns is achieved...
基金supported by NSFC (the National Natural Science Foundation of China) [81273126, 30972454]the Key Project of Guangdong Natural Science Foundation [S2012020010903]+2 种基金the Project of Shenzhen Basic Research Plan [JCYJ20120616 154222545]the Upgrade Scheme of Shenzhen Municipal Key Laboratory [CXB201005260068A]Medical Scientific Research Foundation of Guangdong Province (A2012577)
文摘Trichloroethylene （TCE） is a major pollutant that affects both occupational and general environments. The liver is an important target organ of TCEE. Substantial efforts and remarkable progress into understanding TCE cytotoxicity have been made in cultured liver cells. However, the molecular mechanisms by which TCE induces hepatotoxicity are not well understood. SET （also known as protein phosphatase 2A inhibitor, 12PP2A, or template-activating factor-I, TAF-D is a nuclear protein that regulates histone modification, gene transcription, DNA replication, nucleosome assembly,
文摘Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory speed.This paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual port content addressable memory(DPCAM).In addition,it proposes a new replacement algorithm based on hardware which is called a near-far access replacement algorithm(NFRA)to reduce the cost overhead of the cache controller and improve the cache access latency.The experimental results indicated that the latency for write and read operations are significantly less in comparison with a set-associative cache memory.Moreover,it was shown that a latency of a read operation is nearly constant regardless of the size of DPCAM.However,an estimation of the power dissipation showed that DPCAM consumes about 7%greater than a set-associative cache memory of the same size.These results encourage for embedding DPCAM within the multicore processors as a small shared cache memory.
基金supported jointly by the National Key Research and Development Program of China under Grant No.2022YFB4500303the National Natural Science Foundation of China under Grant Nos.62072198,61825202,and 61929103.
文摘Die-stacked dynamic random access memory(DRAM)caches are increasingly advocated to bridge the performance gap between the on-chip cache and the main memory.To fully realize their potential,it is essential to improve DRAM cache hit rate and lower its cache hit latency.In order to take advantage of the high hit-rate of set-association and the low hit latency of direct-mapping at the same time,we propose a partial direct-mapped die-stacked DRAM cache called P3DC.This design is motivated by a key observation,i.e.,applying a unified mapping policy to different types of blocks cannot achieve a high cache hit rate and low hit latency simultaneously.To address this problem,P3DC classifies data blocks into leading blocks and following blocks,and places them at static positions and dynamic positions,respectively,in a unified set-associative structure.We also propose a replacement policy to balance the miss penalty and the temporal locality of different blocks.In addition,P3DC provides a policy to mitigate cache thrashing due to block type variations.Experimental results demonstrate that P3DC can reduce the cache hit latency by 20.5%while achieving a similar cache hit rate compared with typical set-associative caches.P3DC improves the instructions per cycle(IPC)by up to 66%(12%on average)compared with the state-of-the-art direct-mapped cache—BEAR,and by up to 19%(6%on average)compared with the tag-data decoupled set-associative cache—DEC-A8.
