为提升FPGA(Field Programmable Gate Array)高速Serdes通讯稳定性,实时监控其通讯状态,文中设计了一种基于K码控制字符的通讯协议。创建标志用户数据帧起始的动态SOF(Start of Frame)和标志结束的静态EOF(End of Frame)两种K码控制字符...为提升FPGA(Field Programmable Gate Array)高速Serdes通讯稳定性,实时监控其通讯状态,文中设计了一种基于K码控制字符的通讯协议。创建标志用户数据帧起始的动态SOF(Start of Frame)和标志结束的静态EOF(End of Frame)两种K码控制字符,有利于通讯的连续性检测。创建TLINK(Transmit Link)、BLINK(Back Link)的K码控制字符,其中TLINK控制字符在Serdes的发送端进行定期发送,接收端收到TLINK控制字符后,控制本方的Serdes发送端优先输出BLINK控制字符进行应答,以建立通讯双方之间的握手关系,有利于通讯的超时和状态检测。校验独立于SOF、EOF之间的用户数据,进行CRC32(Cyclic Redundancy Check32)计算,有利于通讯的误码检测。实验结果表明,该协议可实现对Serdes链路的丢帧数量、误码数量、超时数量及通讯断开时长进行准确监控,最小时间精度为10μs。展开更多
在高速SerDes系统中,随着数据传输速率越来越高,信道对数据高频分量的衰减越来越严重。为解决传统连续时间线性均衡器(Continuous Time Linear Equalizer,CTLE)高频补偿能力欠缺和无法适应不同信道衰减的问题,该文在传统CTLE的基础上,...在高速SerDes系统中,随着数据传输速率越来越高,信道对数据高频分量的衰减越来越严重。为解决传统连续时间线性均衡器(Continuous Time Linear Equalizer,CTLE)高频补偿能力欠缺和无法适应不同信道衰减的问题,该文在传统CTLE的基础上,级联低频均衡器,该均衡器采用双路源极负反馈电阻电容差分结构,对低频信号实现补偿的同时,通过源极负反馈电阻和电容引入了一对零极点,可实现对高频信号的二次补偿;同时,该CTLE的源极负反馈电阻电容可调,可实现零极点位置改变,产生不同的增益补偿,达到适应不同信道衰减的目的。在TSMC 28 nm CMOS工艺下,该CTLE在数据传输速率12.5 Gbps下高频补偿最高达20.5 dB,均衡范围为15.4~20.5 dB,眼图的平均张开度可达到0.92 UI。展开更多
In DSP-based SerDes application,it is essential for AFE to implement a pre-ADC equalization to provide a better sig-nal for ADC and DSP.To meet the various equalization requirements of different channel and transmitte...In DSP-based SerDes application,it is essential for AFE to implement a pre-ADC equalization to provide a better sig-nal for ADC and DSP.To meet the various equalization requirements of different channel and transmitter configurations,this paper presents a 112 Gbps DSP-Based PAM4 SerDes receiver with a wide band equalization tuning AFE.The AFE is realized by implementing source degeneration transconductance,feedforward high-pass branch and inductive feedback peaking TIA.The AFE offers a flexible equalization gain tuning of up to 17.5 dB at Nyquist frequency without affecting the DC gain.With the pro-posed AFE,the receiver demonstrates eye opening after digital FIR equalization and achieves 6×10^(-9) BER with a 29.6 dB inser-tion loss channel.展开更多
文章针对56 Gbps至112 Gbps高速SERDES接口在时钟恢复精度与信号完整性方面的关键问题,重点研究接收链路中自适应均衡、双环路时钟数据恢复(Clock and Data Recovery,CDR)及多相位时钟选择等核心电路。通过设计混合均衡结构以补偿信道损...文章针对56 Gbps至112 Gbps高速SERDES接口在时钟恢复精度与信号完整性方面的关键问题,重点研究接收链路中自适应均衡、双环路时钟数据恢复(Clock and Data Recovery,CDR)及多相位时钟选择等核心电路。通过设计混合均衡结构以补偿信道损耗,采用双环路CDR协同多相位选择策略提升时钟抖动抑制能力,实现了亚单位间隔级时序控制。研究结果表明,所提出的电路结构在高速率下能有效降低误码率,显著提升系统传输可靠性。展开更多
基金supported by National Key R&D Program of China No.2022YFB2803401.
文摘In DSP-based SerDes application,it is essential for AFE to implement a pre-ADC equalization to provide a better sig-nal for ADC and DSP.To meet the various equalization requirements of different channel and transmitter configurations,this paper presents a 112 Gbps DSP-Based PAM4 SerDes receiver with a wide band equalization tuning AFE.The AFE is realized by implementing source degeneration transconductance,feedforward high-pass branch and inductive feedback peaking TIA.The AFE offers a flexible equalization gain tuning of up to 17.5 dB at Nyquist frequency without affecting the DC gain.With the pro-posed AFE,the receiver demonstrates eye opening after digital FIR equalization and achieves 6×10^(-9) BER with a 29.6 dB inser-tion loss channel.
文摘文章针对56 Gbps至112 Gbps高速SERDES接口在时钟恢复精度与信号完整性方面的关键问题,重点研究接收链路中自适应均衡、双环路时钟数据恢复(Clock and Data Recovery,CDR)及多相位时钟选择等核心电路。通过设计混合均衡结构以补偿信道损耗,采用双环路CDR协同多相位选择策略提升时钟抖动抑制能力,实现了亚单位间隔级时序控制。研究结果表明,所提出的电路结构在高速率下能有效降低误码率,显著提升系统传输可靠性。
