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Design and optimization of a gate-controlled dual direction electro-static discharge device for an industry-level fluorescent optical fiber temperature sensor
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作者 Yang WANG Xiangliang JIN +5 位作者 Jian YANG Feng YAN Yujie LIU Yan PENG Jun LUO Jun YANG 《Frontiers of Information Technology & Electronic Engineering》 SCIE EI CSCD 2022年第1期158-170,共13页
The input/output(I/O)pins of an industry-level fluorescent optical fiber temperature sensor readout circuit need on-chip integrated high-performance electro-static discharge(ESD)protection devices.It is difficult for ... The input/output(I/O)pins of an industry-level fluorescent optical fiber temperature sensor readout circuit need on-chip integrated high-performance electro-static discharge(ESD)protection devices.It is difficult for the failure level of basic N-type buried layer gate-controlled silicon controlled rectifier(NBL-GCSCR)manufactured by the 0.18µm standard bipolar-CMOS-DMOS(BCD)process to meet this need.Therefore,we propose an on-chip integrated novel deep N-well gate-controlled SCR(DNW-GCSCR)with a high failure level to effectively solve the problems based on the same semiconductor process.Technology computer-aided design(TCAD)simulation is used to analyze the device characteristics.SCRs are tested by transmission line pulses(TLP)to obtain accurate ESD parameters.The holding voltage(24.03 V)of NBL-GCSCR with the longitudinal bipolar junction transistor(BJT)path is significantly higher than the holding voltage(5.15 V)of DNW-GCSCR with the lateral SCR path of the same size.However,the failure current of the NBL-GCSCR device is 1.71 A,and the failure current of the DNW-GCSCR device is 20.99 A.When the gate size of DNW-GCSCR is increased from 2µm to 6µm,the holding voltage is increased from 3.50 V to 8.38 V.The optimized DNW-GCSCR(6µm)can be stably applied on target readout circuits for on-chip electrostatic discharge protection. 展开更多
关键词 Electric breakdown semiconductor device reliability CMOS technology
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The storage lifetime model based on multi-performance degradation parameters
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作者 齐浩淳 张小玲 +1 位作者 谢雪松 吕长志 《Journal of Semiconductors》 EI CAS CSCD 2014年第10期80-84,共5页
According to the multi-performance degradation of the bipolar transistor in the accelerating storage process, an extrapolation model of the storage lifetime is proposed. In this model, using the Wiener process simu- l... According to the multi-performance degradation of the bipolar transistor in the accelerating storage process, an extrapolation model of the storage lifetime is proposed. In this model, using the Wiener process simu- lates the mono-degradation process of each feature degradation; using the copula function describes the correlation among these feature degradations. The Wiener process and parameters in the copula function are considered to associate with the temperature, and their relationships can be represented by the converted equations. Through the maximum likelihood estimation, the parameters in the Wiener process can be found; introducing Kendall's tau, those in the copula function can be estimated. By conducting the regression analyses of the estimated values of the parameters in each stress, their corresponding converted equations can be shown. Based on the storage test data of bipolar transistors, with the estimation method, the storage lifetime is found. The findings show that the model is reasonable for the prediction of storage lifetime. 展开更多
关键词 semiconductor device reliability lifetime estimation prediction methods
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