Wet thermal annealing effects on the properties of TaN/HfO2/Ge metal-oxide-semiconductor （MOS） structures with and without a GeO2 passivation layer are investigated. The physical and the electrical properties are ch...Wet thermal annealing effects on the properties of TaN/HfO2/Ge metal-oxide-semiconductor （MOS） structures with and without a GeO2 passivation layer are investigated. The physical and the electrical properties are characterized by X-ray photoemission spectroscopy, high-resolution transmission electron microscopy, capacitance-voltage （C-V） and current-voltage characteristics. It is demonstrated that wet thermal annealing at relatively higher temperature such as 550 ℃ can lead to Ge incorporation in HfO2 and the partial crystallization of HfO2, which should be responsible for the serious degradation of the electrical characteristics of the TaN/HfO2/Ge MOS capacitors. However, wet thermal annealing at 400 ℃ can decrease the GeOx interlayer thickness at the HfO2/Ge interface, resulting in a significant reduction of the interface states and a smaller effective oxide thickness, along with the introduction of a positive charge in the dielectrics due to the hydrolyzable property of GeOx in the wet ambient. The pre-growth of a thin GeO2 passivation layer can effectively suppress the interface states and improve the C V characteristics for the as-prepared HfO2 gated Ge MOS capacitors, but it also dissembles the benefits of wet thermal annealing to a certain extent.展开更多
In silicon photonics, the carrier depletion scheme has been the most commonly used mechanism for demonstrat- ing high-speed electro-optic modulation. However, in terms of phase modulation efficiency, carrier- accumnla...In silicon photonics, the carrier depletion scheme has been the most commonly used mechanism for demonstrat- ing high-speed electro-optic modulation. However, in terms of phase modulation efficiency, carrier- accumnlation-based devices potentially offer almost an order of carrier depletion. Previously reported accumulation modulator magnitude improvement over those based on designs only considered vertical metal-oxide- semiconductor （MOS） capacitors, which imposes serious restrictions on the design flexibility and integratability with other photonic components. In this work, for the first time to our knowledge, we report experimental demonstration of an all-silicon accumulation phase modulator based on a lateral MOS capacitor. Using a Mach-Zehnder interferometer modulator with a 500-μm-long phase shifter, we demonstrate high-speed modulation up to 25 Gbit/s with a modulation efficiency （V πLπ） of 1.53 V·cm.展开更多
We have investigated the temperature dependent interfacial and electrical characteristics of p-GaAs metal-oxide-semiconductor capacitors during atomic layer deposition （ALD） and annealing of HfO2 using the tetrakis ...We have investigated the temperature dependent interfacial and electrical characteristics of p-GaAs metal-oxide-semiconductor capacitors during atomic layer deposition （ALD） and annealing of HfO2 using the tetrakis （ethylmethyl） amino hafnium precursor. The leakage current decreases with the increase of the ALD tem- perature and the lowest current is obtained at 300 ℃ as a result of the Frenkel-Poole conduction induced leakage current being greatly weakened by the reduction of interfacial oxides at the higher temperature. Post deposition annealing （PDA） at 500 ℃ after ALD at 300 ℃ leads to the lowest leakage current compared with other annealing temperatures. A pronounced reduction in As oxides during PDA at 500 ℃ has been observed using X-ray pho- toelectron spectroscopy at the interface resulting in a proportional increase in Ga203. The increment of Ga203 after PDA depends on the amount of residual As oxides after ALD. Thus, the ALD temperature plays an important role in determining the high-k/GaAs interface condition. Meanwhile, an optimum PDA temperature is essential for obtaining good dielectric properties.展开更多
The interface properties and electrical characteristics of the n-type 4H-SiC planar and trench metal-oxide-semiconductor （MOS） capacitors are investigated by measuring the capacitance voltage and current voltage. Th...The interface properties and electrical characteristics of the n-type 4H-SiC planar and trench metal-oxide-semiconductor （MOS） capacitors are investigated by measuring the capacitance voltage and current voltage. The flat-band voltage and interface state density are evaluated by the quasi-static method. It is not effective on further improving the interface properties annealing at 1250 ℃ in NO ambient for above 1 h due to the increasing interface shallow and fast states. These shallow states reduce the effective positive fixed charge density in the oxide. For the vertical MOS capacitors on the （1120） and （1100） faces, the interface state density can be reduced by approximately one order of magnitude, in comparison to the result of the planar MOS capacitors on the （0001） face under the same NO annealing condition. In addition, it is found that Fowler-Nordheim tunneling current occurs at an oxide electric field of 7 MV/cm for the planar MOS device. However, Poole-Frenkel conduction current occurs at a lower electric field of 4 MV/cm for the trench MOS capacitor. This is due to the local field crowded at the trench corner severely causing the electrons to be early captured at or emitted from the SiO2/SiC interface. These results provide a reference for an in-depth understanding of the mobility-limiting factors and long term reliability of the trench and planar SiO2/SiC interfaces.展开更多
A 4H-silicon carbide metal-insulator-semiconductor structure with ultra-thin Al2O3 as the gate dielectric, deposited by atomic layer deposition on tile epitaxial layer of a 4H-SiC （0001） 80N-/N＋ substrate, has been...A 4H-silicon carbide metal-insulator-semiconductor structure with ultra-thin Al2O3 as the gate dielectric, deposited by atomic layer deposition on tile epitaxial layer of a 4H-SiC （0001） 80N-/N＋ substrate, has been fabricated. The experimental results indicate that the prepared ultra-thin Al2O3 gate dielectric exhibits good physical and electrical characteristics, including a high breakdown electrical field of 25 MV/cm, excellent interface properties （1 × 10^14 cm^-2） and low gate-leakage current （IG = 1 × 10^-3 A/cm 2@Eox = 8 MV/cm）. Analysis of the current conduction mecha- nism on the deposited Al2O3 gate dielectric was also systematically performed. The confirmed conduction mechanisms consisted of Fowler-Nordheim （FN） tuaneling, the Frenkel-Poole mechanism, direct tunneling and Schottky emission, and the dominant current conduction mechanism depends on the applied electrical field. When the gate leakage current mechanism is dominated by FN tunneling, the barrier height of SiC/Al2O3 is 1.4 eV, which can meet the requirements of silicon carbide metal-insulator-semiconductor transistor devices.展开更多
The paper reports that Hfrio dielectric is deposited by reactive co-sputtering of Hf and Ti targets in an Ar/O2 ambience, followed by an annealing in different gas ambiences of N2, NO and NH3 at 600℃ for 2 min. Capac...The paper reports that Hfrio dielectric is deposited by reactive co-sputtering of Hf and Ti targets in an Ar/O2 ambience, followed by an annealing in different gas ambiences of N2, NO and NH3 at 600℃ for 2 min. Capacitancevoltage and gate-leakage properties are characterized and compared. The results indicate that the NO-annealed sample exhibits the lowest interface-state and dielectric-charge densities and best device reliability. This is attributed to the fact that nitridation can create strong Si≡N bonds to passivate dangling Si bonds and replace strained Si-O bonds, thus the sample forms a hardened dielectric/Si interface with high reliability.展开更多
Pd-Al2O3-Si capacitors with Ru nanocrystals are fabricated and electrically characterized for nonvolatile memory application. While keeping the entire insulator Al2O3 thickness fixed, the memory window has a strong de...Pd-Al2O3-Si capacitors with Ru nanocrystals are fabricated and electrically characterized for nonvolatile memory application. While keeping the entire insulator Al2O3 thickness fixed, the memory window has a strong dependence on the tunneling layer thickness under low operating voltages, whereas it has weak dependence under high operating voltages. As for the optimal configuration comprised of 6-nm tunneling layer and 22-nm blocking layer, the resulting memory window increases from 1.5 V to 5.3 V with bias pulse increasing from 10-5 s to 10-2 s under ±7 V. A ten-year memory window as large as 5.2 V is extrapolated at room temperature after ±8 V/1 ms programming/erasing pulses.展开更多
The response characteristics of resistance is observed by the analysis of experimental data of micro scale semiconductor bridge （MSCB） under different voltage inputs. Two critical voltages are found. One is called e...The response characteristics of resistance is observed by the analysis of experimental data of micro scale semiconductor bridge （MSCB） under different voltage inputs. Two critical voltages are found. One is called exploding voltage, above which the MSCB can be melted and vaporized without generating a plasma, and the other is called producing a plasma voltage, above which the MSCB is entirely vaporized, and then the current flows through the vapor producing the plasma. Based on the non Fourier heat conduction theory, the electrothermal energy conversion model is es tablished for the stage from heating to exploding, and then the correlation of MSCB and time is ob tained by graphic calculation. Importantly, the critical exploding voltage and exploding time are also derivate. With the comparison between the analytical result from the theoretical model and that from experimental data, it has been demonstrated that the theoretical model is reasonable and feasible for designing the exploding voltage and exploding time.展开更多
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 61176092,61036003,and 60837001)the National Basic Research Program of China (Grant No. 2012CB933503)+1 种基金the Ph.D. Program Foundation of Ministry of Education of China (Grant No. 20110121110025)the Fundamental Research Funds for the Central Universities,China (Grant No. 2010121056)
文摘Wet thermal annealing effects on the properties of TaN/HfO2/Ge metal-oxide-semiconductor （MOS） structures with and without a GeO2 passivation layer are investigated. The physical and the electrical properties are characterized by X-ray photoemission spectroscopy, high-resolution transmission electron microscopy, capacitance-voltage （C-V） and current-voltage characteristics. It is demonstrated that wet thermal annealing at relatively higher temperature such as 550 ℃ can lead to Ge incorporation in HfO2 and the partial crystallization of HfO2, which should be responsible for the serious degradation of the electrical characteristics of the TaN/HfO2/Ge MOS capacitors. However, wet thermal annealing at 400 ℃ can decrease the GeOx interlayer thickness at the HfO2/Ge interface, resulting in a significant reduction of the interface states and a smaller effective oxide thickness, along with the introduction of a positive charge in the dielectrics due to the hydrolyzable property of GeOx in the wet ambient. The pre-growth of a thin GeO2 passivation layer can effectively suppress the interface states and improve the C V characteristics for the as-prepared HfO2 gated Ge MOS capacitors, but it also dissembles the benefits of wet thermal annealing to a certain extent.
基金Engineering and Physical Sciences Research Council(EPSRC)(EP/M008975/1,EP/M009416/1,EP/N013247/1,EP/R003076/1)EU Seventh Framework Programme(FP7)Marie-Curie Carrier-Integration-Grant(PCIG13-GA-2013-618116)
文摘In silicon photonics, the carrier depletion scheme has been the most commonly used mechanism for demonstrat- ing high-speed electro-optic modulation. However, in terms of phase modulation efficiency, carrier- accumnlation-based devices potentially offer almost an order of carrier depletion. Previously reported accumulation modulator magnitude improvement over those based on designs only considered vertical metal-oxide- semiconductor （MOS） capacitors, which imposes serious restrictions on the design flexibility and integratability with other photonic components. In this work, for the first time to our knowledge, we report experimental demonstration of an all-silicon accumulation phase modulator based on a lateral MOS capacitor. Using a Mach-Zehnder interferometer modulator with a 500-μm-long phase shifter, we demonstrate high-speed modulation up to 25 Gbit/s with a modulation efficiency （V πLπ） of 1.53 V·cm.
基金supported by the Advance Research Project of China(No.5130803XXXX)the National Natural Science Foundation of China(No.61176070)
文摘We have investigated the temperature dependent interfacial and electrical characteristics of p-GaAs metal-oxide-semiconductor capacitors during atomic layer deposition （ALD） and annealing of HfO2 using the tetrakis （ethylmethyl） amino hafnium precursor. The leakage current decreases with the increase of the ALD tem- perature and the lowest current is obtained at 300 ℃ as a result of the Frenkel-Poole conduction induced leakage current being greatly weakened by the reduction of interfacial oxides at the higher temperature. Post deposition annealing （PDA） at 500 ℃ after ALD at 300 ℃ leads to the lowest leakage current compared with other annealing temperatures. A pronounced reduction in As oxides during PDA at 500 ℃ has been observed using X-ray pho- toelectron spectroscopy at the interface resulting in a proportional increase in Ga203. The increment of Ga203 after PDA depends on the amount of residual As oxides after ALD. Thus, the ALD temperature plays an important role in determining the high-k/GaAs interface condition. Meanwhile, an optimum PDA temperature is essential for obtaining good dielectric properties.
基金supported by the National Basic Research Program of China(Grant No.2015CB759600)the National Natural Science Foundation of China(Grant Nos.61474113 and 61574140)+3 种基金the Beijing NOVA Program,China(Grant No.Z1611000049161132016071)China Academy of Engineering Physics(CAEP)Microsystem and THz Science and Technology Foundation,China(Grant No.CAEPMT201502)the Beijing Municipal Science and Technology Commission Project,China(Grant Nos.Z161100002116018 and D16110300430000)the Youth Innovation Promotion Association of Chinese Academy of Sciences(Grant No.2012098)
文摘The interface properties and electrical characteristics of the n-type 4H-SiC planar and trench metal-oxide-semiconductor （MOS） capacitors are investigated by measuring the capacitance voltage and current voltage. The flat-band voltage and interface state density are evaluated by the quasi-static method. It is not effective on further improving the interface properties annealing at 1250 ℃ in NO ambient for above 1 h due to the increasing interface shallow and fast states. These shallow states reduce the effective positive fixed charge density in the oxide. For the vertical MOS capacitors on the （1120） and （1100） faces, the interface state density can be reduced by approximately one order of magnitude, in comparison to the result of the planar MOS capacitors on the （0001） face under the same NO annealing condition. In addition, it is found that Fowler-Nordheim tunneling current occurs at an oxide electric field of 7 MV/cm for the planar MOS device. However, Poole-Frenkel conduction current occurs at a lower electric field of 4 MV/cm for the trench MOS capacitor. This is due to the local field crowded at the trench corner severely causing the electrons to be early captured at or emitted from the SiO2/SiC interface. These results provide a reference for an in-depth understanding of the mobility-limiting factors and long term reliability of the trench and planar SiO2/SiC interfaces.
基金supported by the 2010 School Fundamental Scientific Research Fund of Xidian University (Grant No. K50510250008)
文摘A 4H-silicon carbide metal-insulator-semiconductor structure with ultra-thin Al2O3 as the gate dielectric, deposited by atomic layer deposition on tile epitaxial layer of a 4H-SiC （0001） 80N-/N＋ substrate, has been fabricated. The experimental results indicate that the prepared ultra-thin Al2O3 gate dielectric exhibits good physical and electrical characteristics, including a high breakdown electrical field of 25 MV/cm, excellent interface properties （1 × 10^14 cm^-2） and low gate-leakage current （IG = 1 × 10^-3 A/cm 2@Eox = 8 MV/cm）. Analysis of the current conduction mecha- nism on the deposited Al2O3 gate dielectric was also systematically performed. The confirmed conduction mechanisms consisted of Fowler-Nordheim （FN） tuaneling, the Frenkel-Poole mechanism, direct tunneling and Schottky emission, and the dominant current conduction mechanism depends on the applied electrical field. When the gate leakage current mechanism is dominated by FN tunneling, the barrier height of SiC/Al2O3 is 1.4 eV, which can meet the requirements of silicon carbide metal-insulator-semiconductor transistor devices.
基金Project supported by the National Natural Science Foundation of China （Grant No 60376019）.
文摘The paper reports that Hfrio dielectric is deposited by reactive co-sputtering of Hf and Ti targets in an Ar/O2 ambience, followed by an annealing in different gas ambiences of N2, NO and NH3 at 600℃ for 2 min. Capacitancevoltage and gate-leakage properties are characterized and compared. The results indicate that the NO-annealed sample exhibits the lowest interface-state and dielectric-charge densities and best device reliability. This is attributed to the fact that nitridation can create strong Si≡N bonds to passivate dangling Si bonds and replace strained Si-O bonds, thus the sample forms a hardened dielectric/Si interface with high reliability.
基金Project supported by the National Key Technology Research and Development Program of China(Grant No.2009ZX02302-002)the National Natural Science Foundation of China(Grant No.61274088)the Program for New Century Excellent Talents in University of Ministry of Education of China(Grant No.NCET-08-0127)
文摘Pd-Al2O3-Si capacitors with Ru nanocrystals are fabricated and electrically characterized for nonvolatile memory application. While keeping the entire insulator Al2O3 thickness fixed, the memory window has a strong dependence on the tunneling layer thickness under low operating voltages, whereas it has weak dependence under high operating voltages. As for the optimal configuration comprised of 6-nm tunneling layer and 22-nm blocking layer, the resulting memory window increases from 1.5 V to 5.3 V with bias pulse increasing from 10-5 s to 10-2 s under ±7 V. A ten-year memory window as large as 5.2 V is extrapolated at room temperature after ±8 V/1 ms programming/erasing pulses.
基金Supported by the National Basic Research Program of China("973"Program)(51299)
文摘The response characteristics of resistance is observed by the analysis of experimental data of micro scale semiconductor bridge （MSCB） under different voltage inputs. Two critical voltages are found. One is called exploding voltage, above which the MSCB can be melted and vaporized without generating a plasma, and the other is called producing a plasma voltage, above which the MSCB is entirely vaporized, and then the current flows through the vapor producing the plasma. Based on the non Fourier heat conduction theory, the electrothermal energy conversion model is es tablished for the stage from heating to exploding, and then the correlation of MSCB and time is ob tained by graphic calculation. Importantly, the critical exploding voltage and exploding time are also derivate. With the comparison between the analytical result from the theoretical model and that from experimental data, it has been demonstrated that the theoretical model is reasonable and feasible for designing the exploding voltage and exploding time.
