The structure of the tissues is formed in a self-similar manner, forming fractal structures in their transport networks. The structure exhibits allometric forming and so-called scaling behavior. This is a basic growth...The structure of the tissues is formed in a self-similar manner, forming fractal structures in their transport networks. The structure exhibits allometric forming and so-called scaling behavior. This is a basic growth model fine-tuned by various connections of the cells (junctions and adherent connections), intended to direct material and energy transports between them. This secondary control of cell metabolism decreases primary metabolic transport through the free surfaces of the cells. The cellular network is formed by triggering the endogenous electric fields, which are dominantly governed by cell membrane potential. Proliferation exhibits a different electric pattern due to the low cell-membrane potential and resulting negativity relative to its environment. This potential change characterizes cells in normal proliferation and a cluster of cells (a tumor) in the case of cancerous development. This latter has certain similarities to the leakage transport of liquid in porous media, substituting the pressure with endogenous tumor potential. The average survival of a tumor depends on the kind of available metabolic transport and the fractal dimensions of the newly built angiogenic network.展开更多
This paper introduces ARCtimer, a framework for modeling, generating, verifying, and enforcing timing constraints for individual self-timed handshake components. The constraints guarantee that the component＇s gate-le...This paper introduces ARCtimer, a framework for modeling, generating, verifying, and enforcing timing constraints for individual self-timed handshake components. The constraints guarantee that the component＇s gate-level circuit implementation obeys the component＇s handshake protocol specification. Because the handshake protocols are delayinsensitive, self-timed systems built using ARCtimer-verified components are also delay-insensitive. By carefully considering time locally, we can ignore time globally. ARCtimer comes early in the design process as part of building a library of verified components for later system use. The library also stores static timing analysis （STA） code to validate and enforce the component＇s constraints in any self-timed system built using the library. The library descriptions of a handshake component＇s circuit, protocol, timing constraints, and STA code are robust to circuit modifications applied later in the design process by technology mapping or layout tools. In addition to presenting new work and discussing related work, this paper identifies critical choices and explains what modular timing verification entails and how it works.展开更多
This paper proposes a new optimization method to improve the performance of a null convention logic asynchronous pipeline.Parallel combinational logic modules in the pipelines can work alternately in null and data cyc...This paper proposes a new optimization method to improve the performance of a null convention logic asynchronous pipeline.Parallel combinational logic modules in the pipelines can work alternately in null and data cycles by using a parallel processing mode.The complete waiting time for both null and data signals of combinational logic output in previous asynchronous register stage is reduced by decoupling the output from combinational logic modules.Performance penalty brought by null cycle is reduced while the data processing capacity is increased.The novel asynchronous pipeline based on asynchronous full adders with different bit widths as asynchronous combination logic modules is simulated using 0.18-μm CMOS technology.Based on 6 bits asynchronous adder as asynchronous combination logic modules, the simulation result of this new pipeline proposal demonstrates a high throughput up to 72.4% improvement with appropriate power consumption.This indicates the new design proposal is preferable for high-speed as ynchronous designs due to its high throughput and delay-insensitivity.展开更多
A 14-bit low power self-timed differential successive approximation（SAR） ADC with an on-chip multisegment bandgap reference（BGR） is described.An on-chip multi-segment BGR,which has a temperature coefficient of 1.3...A 14-bit low power self-timed differential successive approximation（SAR） ADC with an on-chip multisegment bandgap reference（BGR） is described.An on-chip multi-segment BGR,which has a temperature coefficient of 1.3 ppm/℃and a thermal drift of about 100μV over the temperature range of -40 to 120℃is implemented to provide a high precision reference voltage for the SAR ADC.The Gray code form is utilized instead of binary form mode control to reduce substrate noise and enhance the linearity of the whole system.Self-timed bit-cycling is adopted to enhance the time efficiency.The 14-bit ADC was fabricated in a TSMC 0.13μm CMOS process. With the on-chip BGR,the SAR ADC achieves an SNDR of 81.2 dB（13.2 ENOB） and an SFDR of 85.2 dB with a conversion rate of 2 MS/s at room temperature and can keep an ENOB of more than 12 bits at a conversion rate of 2 MS/s over the temperature range from -40 to 120℃.展开更多
文摘The structure of the tissues is formed in a self-similar manner, forming fractal structures in their transport networks. The structure exhibits allometric forming and so-called scaling behavior. This is a basic growth model fine-tuned by various connections of the cells (junctions and adherent connections), intended to direct material and energy transports between them. This secondary control of cell metabolism decreases primary metabolic transport through the free surfaces of the cells. The cellular network is formed by triggering the endogenous electric fields, which are dominantly governed by cell membrane potential. Proliferation exhibits a different electric pattern due to the low cell-membrane potential and resulting negativity relative to its environment. This potential change characterizes cells in normal proliferation and a cluster of cells (a tumor) in the case of cancerous development. This latter has certain similarities to the leakage transport of liquid in porous media, substituting the pressure with endogenous tumor potential. The average survival of a tumor depends on the kind of available metabolic transport and the fractal dimensions of the newly built angiogenic network.
基金This work was supported by the National Natural Science Foundation of China under Grant No. 61402121.
文摘This paper introduces ARCtimer, a framework for modeling, generating, verifying, and enforcing timing constraints for individual self-timed handshake components. The constraints guarantee that the component＇s gate-level circuit implementation obeys the component＇s handshake protocol specification. Because the handshake protocols are delayinsensitive, self-timed systems built using ARCtimer-verified components are also delay-insensitive. By carefully considering time locally, we can ignore time globally. ARCtimer comes early in the design process as part of building a library of verified components for later system use. The library also stores static timing analysis （STA） code to validate and enforce the component＇s constraints in any self-timed system built using the library. The library descriptions of a handshake component＇s circuit, protocol, timing constraints, and STA code are robust to circuit modifications applied later in the design process by technology mapping or layout tools. In addition to presenting new work and discussing related work, this paper identifies critical choices and explains what modular timing verification entails and how it works.
基金supported by the National Science Fund for Distinguished Young Scholars (No. 60725415)the National Natural Science Foundation of China (Nos. 60676009, 90407016)
文摘This paper proposes a new optimization method to improve the performance of a null convention logic asynchronous pipeline.Parallel combinational logic modules in the pipelines can work alternately in null and data cycles by using a parallel processing mode.The complete waiting time for both null and data signals of combinational logic output in previous asynchronous register stage is reduced by decoupling the output from combinational logic modules.Performance penalty brought by null cycle is reduced while the data processing capacity is increased.The novel asynchronous pipeline based on asynchronous full adders with different bit widths as asynchronous combination logic modules is simulated using 0.18-μm CMOS technology.Based on 6 bits asynchronous adder as asynchronous combination logic modules, the simulation result of this new pipeline proposal demonstrates a high throughput up to 72.4% improvement with appropriate power consumption.This indicates the new design proposal is preferable for high-speed as ynchronous designs due to its high throughput and delay-insensitivity.
文摘A 14-bit low power self-timed differential successive approximation（SAR） ADC with an on-chip multisegment bandgap reference（BGR） is described.An on-chip multi-segment BGR,which has a temperature coefficient of 1.3 ppm/℃and a thermal drift of about 100μV over the temperature range of -40 to 120℃is implemented to provide a high precision reference voltage for the SAR ADC.The Gray code form is utilized instead of binary form mode control to reduce substrate noise and enhance the linearity of the whole system.Self-timed bit-cycling is adopted to enhance the time efficiency.The 14-bit ADC was fabricated in a TSMC 0.13μm CMOS process. With the on-chip BGR,the SAR ADC achieves an SNDR of 81.2 dB（13.2 ENOB） and an SFDR of 85.2 dB with a conversion rate of 2 MS/s at room temperature and can keep an ENOB of more than 12 bits at a conversion rate of 2 MS/s over the temperature range from -40 to 120℃.
