The rapid proliferation of Internet of Things(IoT)devices necessitates lightweight cryptographic algorithms and their secure physical implementations.Masking,as a provably secure countermeasure against Side-Channel At...The rapid proliferation of Internet of Things(IoT)devices necessitates lightweight cryptographic algorithms and their secure physical implementations.Masking,as a provably secure countermeasure against Side-Channel Attacks(SCA),has been extensively studied in the context of lightweight cryptography algorithms.Currently,some cryptographers have proposed a low-cost Threshold Implementation(TI)of the uBlock algorithm.However,their approach suffers from significant area overhead due to the inefficient serial and pipelined implementation of uBlock’s Pshufb-Xor(PX)network structure.To address this issue,we develop a new serial and pipelined implementation method that optimizes the area of the uBlock algorithm.Based on this optimization,we implement a 2-share TI scheme for uBlock that requires minimal area resources and does not need fresh randomness.Compared to the state-of-the-art appoach,our method reduces slice area by 63.4%on Field Programmable Gate Arrays(FPGA)platform and Gate Equivalent(GE)area by 17.2%on Application-Specific Integrated Circuit(ASIC)platform for the unprotected implementation.For the protected implementation,our method reduces slice area by 41.5%and GE area by 14.0%.Finally,our protection scheme is validated using the automated tool PROLEAD and evaluated with Test Vector Leakage Assessment(TVLA),achieving first-order glitch-extended probing security.展开更多
Keccak算法作为新一代Hash函数新标准SHA-3后,其安全性受到业界的广泛关注.针对Keccak算法提供掩码防护以抵御差分功耗攻击(differential power analysis,DPA)是目前的研究热点之一.现存的Keccak掩码防护方法瓶颈在于其所占用芯片面积...Keccak算法作为新一代Hash函数新标准SHA-3后,其安全性受到业界的广泛关注.针对Keccak算法提供掩码防护以抵御差分功耗攻击(differential power analysis,DPA)是目前的研究热点之一.现存的Keccak掩码防护方法瓶颈在于其所占用芯片面积都很大,且所需额外注入的随机数个数也特别多.如何给出Keccak算法新型的掩码是研究的难点.本文基于Keccak算法的结构和S盒的性质,提出了一个使用3个掩码分量构造抵抗二阶DPA的新型Keccak门限掩码方案,使其所需的掩码分量个数达到最少值.此外,在FPGA平台上实现时,我们采用分时存储线性部件和非线性部件的方法进行优化,从而使该二阶Keccak门限掩码方案所占的芯片面积进一步减少.结果表明,在UMC130 nm工艺库下,并行结构与串行结构所占的芯片面积分别为185.27 kGE及33.87 kGE,且均不需要注入额外的随机数.与已有的掩码方案相比,新的二阶掩码方案在串行和并行结构下,所占的芯片面积及额外注入的随机数个数均显著降低.展开更多
基金supported by the National Key R&D Program of China(No.2022YFB310380).
文摘The rapid proliferation of Internet of Things(IoT)devices necessitates lightweight cryptographic algorithms and their secure physical implementations.Masking,as a provably secure countermeasure against Side-Channel Attacks(SCA),has been extensively studied in the context of lightweight cryptography algorithms.Currently,some cryptographers have proposed a low-cost Threshold Implementation(TI)of the uBlock algorithm.However,their approach suffers from significant area overhead due to the inefficient serial and pipelined implementation of uBlock’s Pshufb-Xor(PX)network structure.To address this issue,we develop a new serial and pipelined implementation method that optimizes the area of the uBlock algorithm.Based on this optimization,we implement a 2-share TI scheme for uBlock that requires minimal area resources and does not need fresh randomness.Compared to the state-of-the-art appoach,our method reduces slice area by 63.4%on Field Programmable Gate Arrays(FPGA)platform and Gate Equivalent(GE)area by 17.2%on Application-Specific Integrated Circuit(ASIC)platform for the unprotected implementation.For the protected implementation,our method reduces slice area by 41.5%and GE area by 14.0%.Finally,our protection scheme is validated using the automated tool PROLEAD and evaluated with Test Vector Leakage Assessment(TVLA),achieving first-order glitch-extended probing security.
