A fast motion estimation algorithm for variable block-size using the ＂line scan and block merge procedure＂ is proposed for airborne image compression modules.Full hardware implementation via FPGA is discussed in det...A fast motion estimation algorithm for variable block-size using the ＂line scan and block merge procedure＂ is proposed for airborne image compression modules.Full hardware implementation via FPGA is discussed in detail.The proposed pipelined architecture based on the line scan algorithm is capable of calculating the required 41 motion vectors of various size blocks supported by H.264 within a 16 × 16 block in parallel.An adaptive rate distortion cost function is used for various size block decision.The motion vectors of adjacent small blocks are merged to predict the motion vectors of larger blocks for reducing computation.Experimental results show that our proposed method has lower computational complexity than full search algorithm with slight quality decrease and little bit rate increase.Due to the high real-time processing speed it can be easily realized in hardware.展开更多
As a general format of the image,bitmap(BMP)image has wide applications,and consequently it is an important part of image processing.By segmenting the bitmap and combining the three-dimesional(3D)model of the discrete...As a general format of the image,bitmap(BMP)image has wide applications,and consequently it is an important part of image processing.By segmenting the bitmap and combining the three-dimesional(3D)model of the discrete algorithm with the scanning line compensation algorithm,a mathematical model is built.According to the topological relations between several control points on the model surface,the surface of the model is discretized,and a planar triangle sequence is used to describe 3D objects.Finally,the bitmap is enlarged by combining the borrowing compensation based on 3D modeling principle of discrete algorithm with the scanning line compensation algorithm of binary lattice image,thus getting a relatively clear enlarged BMP image.展开更多
基金Supported by the Aviation Science Fund of China(2009ZC15001)
文摘A fast motion estimation algorithm for variable block-size using the ＂line scan and block merge procedure＂ is proposed for airborne image compression modules.Full hardware implementation via FPGA is discussed in detail.The proposed pipelined architecture based on the line scan algorithm is capable of calculating the required 41 motion vectors of various size blocks supported by H.264 within a 16 × 16 block in parallel.An adaptive rate distortion cost function is used for various size block decision.The motion vectors of adjacent small blocks are merged to predict the motion vectors of larger blocks for reducing computation.Experimental results show that our proposed method has lower computational complexity than full search algorithm with slight quality decrease and little bit rate increase.Due to the high real-time processing speed it can be easily realized in hardware.
基金National Natural Science Foundation of China(Nos.61162016,61562057)Natural Science Foundation of Gansu Province(No.18JR3RA124)+1 种基金Science and Technology Program Project of Gansu Province(Nos.18JR3RA104,1504FKCA038)Science and Technology Project of Gansu Education Department(No.2017D-08)
文摘As a general format of the image,bitmap(BMP)image has wide applications,and consequently it is an important part of image processing.By segmenting the bitmap and combining the three-dimesional(3D)model of the discrete algorithm with the scanning line compensation algorithm,a mathematical model is built.According to the topological relations between several control points on the model surface,the surface of the model is discretized,and a planar triangle sequence is used to describe 3D objects.Finally,the bitmap is enlarged by combining the borrowing compensation based on 3D modeling principle of discrete algorithm with the scanning line compensation algorithm of binary lattice image,thus getting a relatively clear enlarged BMP image.
