A team of researchers from the University of Science and Technology of China(USTC)of the Chinese Academy of Sciences(CAS)and its partners have made significant advancements in random quantum circuit sampling with Zuch...A team of researchers from the University of Science and Technology of China(USTC)of the Chinese Academy of Sciences(CAS)and its partners have made significant advancements in random quantum circuit sampling with Zuchongzhi-3,a superconducting quantum computing prototype featuring 105 qubits and 182 couplers.展开更多
Cross-entropy benchmarking is a central technique adopted to certify a quantum chip in recent investigations.To better understand its mathematical foundation and develop new benchmarking schemes,the concept of ergodic...Cross-entropy benchmarking is a central technique adopted to certify a quantum chip in recent investigations.To better understand its mathematical foundation and develop new benchmarking schemes,the concept of ergodicity was introduced to random circuit sampling and it was found that the Haar random quantum circuit could satisfy an ergodicity condition—the average of certain types of postprocessing function over the output bit strings is close to the average over the unitary ensemble.For noiseless random circuits,it was proven that the ergodicity holds for polynomials of degree t with positive coefficients when the random circuits form a unitary 2t-design.For strong enough noise,the ergodicity condition is violated,which suggests that ergodicity is a property that can be exploited to certify a quantum chip.The deviation of ergodicity was formulated as a measure for quantum chip benchmarking,and it was demonstrated that it can be used to estimate the circuit fidelity for global depolarizing noise and weakly correlated noise.For a quadratic postprocessing function,our framework recovered Google’s result on estimating the circuit fidelity via linear cross-entropy benchmarking(XEB),and we gave a sufficient condition on the noise model characterizing when such estimation is valid.The results establish an interesting connection between ergodicity and noise in random circuits and provide new insights into designing quantum benchmarking schemes.展开更多
A high performance sample-and-hold （S/H） circuit used in a pipelined analog-to-digital converter （ADC） is presented. Capacitor flip-around architecture is used in this S/H circuit with a novel gain-boosted differe...A high performance sample-and-hold （S/H） circuit used in a pipelined analog-to-digital converter （ADC） is presented. Capacitor flip-around architecture is used in this S/H circuit with a novel gain-boosted differential folded cascode operational transconductance amplifier. A double-bootstrapped switch is designed to improve the performance of the circuit. The circuit is implemented using a 0.18 μm 1P6M CMOS process. Measurement results show that the effective number of bits is 14.03 bits, the spurious free dynamic range is 94.62 dB, the signal to noise and distortion ratio is 86.28 dB, and the total harmonic distortion is -91.84 dB for a 5 MHz input signal with 50 MS/s sampling rate. A pipeline ADC with the designed S/H circuit has been implemented.展开更多
A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-andhold amplifier （SHA） is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to allevi...A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-andhold amplifier （SHA） is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to alleviate the clock skew effect. On-chip bias current is programmable to achieve low power dissipation at different sampling rates. Particularly, drain-to-source voltages in the operational amplifiers （opamps） are fixed to ensure high DC gain within the variant range of the bias current. Both on-chip and off-chip decoupling capacitors are used in the voltage reference circuit in consideration of low power and stability. The proposed ADC was implemented in 0.18-μm 1P6M CMOS technology. With a 2.4-MHz input, the measured peak SNDR and SFDR are 74.4 and 91.6 dB at 2.5 MSample/s, 74.3 and 85.4 dB at 8.0 MSample/s. It consumes 8.1, 21.6, 29.7, and 56.7 mW （including I/O drivers） when operating at 1.5, 2.5, 5.0, and 8.0 MSample/s with 2.7 V power supply, respectively. The chip occupies 3.2 mm^2, including I/O pads.展开更多
文摘A team of researchers from the University of Science and Technology of China(USTC)of the Chinese Academy of Sciences(CAS)and its partners have made significant advancements in random quantum circuit sampling with Zuchongzhi-3,a superconducting quantum computing prototype featuring 105 qubits and 182 couplers.
基金the Sydney Quantum Academy and the support by the National Research Foundation,SingaporeA*STAR under its CQT Bridging Grant and its Quantum Engineering Program under grant NRF2021-QEP2-02-P05+7 种基金F.M.acknowledges the support by City University of Hong Kong(Project No.9610623)the Guangdong Provincial Quantum Science Strategic Initiative(Grant No.GDZX2203001,GDZX2403001)the YTJX academy.M.H.Y.is supported by National Natural Science Foundation of China(11875160 and U1801661)the Natural Science Foundation of Guangdong Province(2017B030308003)the Science,Technology and Innovation Commission of Shenzhen Municipality(JCYJ20170412152620376 and JCYJ20170817105046702 and KYTDPT20181011104202253)the Key R&D Program of Guangdong province(2018B030326001)the Economy,Trade and Information Commission of Shenzhen Municipality(201901161512)Guangdong Provincial Key Laboratory(Grant No.2019B121203002).
文摘Cross-entropy benchmarking is a central technique adopted to certify a quantum chip in recent investigations.To better understand its mathematical foundation and develop new benchmarking schemes,the concept of ergodicity was introduced to random circuit sampling and it was found that the Haar random quantum circuit could satisfy an ergodicity condition—the average of certain types of postprocessing function over the output bit strings is close to the average over the unitary ensemble.For noiseless random circuits,it was proven that the ergodicity holds for polynomials of degree t with positive coefficients when the random circuits form a unitary 2t-design.For strong enough noise,the ergodicity condition is violated,which suggests that ergodicity is a property that can be exploited to certify a quantum chip.The deviation of ergodicity was formulated as a measure for quantum chip benchmarking,and it was demonstrated that it can be used to estimate the circuit fidelity for global depolarizing noise and weakly correlated noise.For a quadratic postprocessing function,our framework recovered Google’s result on estimating the circuit fidelity via linear cross-entropy benchmarking(XEB),and we gave a sufficient condition on the noise model characterizing when such estimation is valid.The results establish an interesting connection between ergodicity and noise in random circuits and provide new insights into designing quantum benchmarking schemes.
基金supported by the National Science and Technology Major Project of China(No.2012ZX03004008)
文摘A high performance sample-and-hold （S/H） circuit used in a pipelined analog-to-digital converter （ADC） is presented. Capacitor flip-around architecture is used in this S/H circuit with a novel gain-boosted differential folded cascode operational transconductance amplifier. A double-bootstrapped switch is designed to improve the performance of the circuit. The circuit is implemented using a 0.18 μm 1P6M CMOS process. Measurement results show that the effective number of bits is 14.03 bits, the spurious free dynamic range is 94.62 dB, the signal to noise and distortion ratio is 86.28 dB, and the total harmonic distortion is -91.84 dB for a 5 MHz input signal with 50 MS/s sampling rate. A pipeline ADC with the designed S/H circuit has been implemented.
文摘A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-andhold amplifier （SHA） is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to alleviate the clock skew effect. On-chip bias current is programmable to achieve low power dissipation at different sampling rates. Particularly, drain-to-source voltages in the operational amplifiers （opamps） are fixed to ensure high DC gain within the variant range of the bias current. Both on-chip and off-chip decoupling capacitors are used in the voltage reference circuit in consideration of low power and stability. The proposed ADC was implemented in 0.18-μm 1P6M CMOS technology. With a 2.4-MHz input, the measured peak SNDR and SFDR are 74.4 and 91.6 dB at 2.5 MSample/s, 74.3 and 85.4 dB at 8.0 MSample/s. It consumes 8.1, 21.6, 29.7, and 56.7 mW （including I/O drivers） when operating at 1.5, 2.5, 5.0, and 8.0 MSample/s with 2.7 V power supply, respectively. The chip occupies 3.2 mm^2, including I/O pads.
