For limited distortion source coding, it is generally considered that the minimum value of the coding average distortion is 0, and the maximum value is the minimum distortion value of making R(D) = 0. This is the defi...For limited distortion source coding, it is generally considered that the minimum value of the coding average distortion is 0, and the maximum value is the minimum distortion value of making R(D) = 0. This is the definition domain of the information rate distortion function. In this paper, the upper and lower bounds of the information rate distortion function R(D) are derived and computed for the typical sources. The results show that the lower bound of the coding average distortion D is related to the symbol distortion function, which can further improve the theory of limited distortion source coding.展开更多
This paper presents a new test data compression/decompression method for SoC testing,called hybrid run length codes. The method makes a full analysis of the factors which influence test parameters：compression ratio,t...This paper presents a new test data compression/decompression method for SoC testing,called hybrid run length codes. The method makes a full analysis of the factors which influence test parameters：compression ratio,test application time, and area overhead. To improve the compression ratio, the new method is based on variable-to-variable run length codes,and a novel algorithm is proposed to reorder the test vectors and fill the unspecified bits in the pre-processing step. With a novel on-chip decoder, low test application time and low area overhead are obtained by hybrid run length codes. Finally, an experimental comparison on ISCAS 89 benchmark circuits validates the proposed method展开更多
This paper is concerned with (3,n) and (4,n) regular quasi-cyclic Low Density Parity Check (LDPC) code constructions from elementary number theory.Given the column weight,we determine the shift values of the circulant...This paper is concerned with (3,n) and (4,n) regular quasi-cyclic Low Density Parity Check (LDPC) code constructions from elementary number theory.Given the column weight,we determine the shift values of the circulant permutation matrices via arithmetic analysis.The proposed constructions of quasi-cyclic LDPC codes achieve the following main advantages simultaneously:1) our methods are constructive in the sense that we avoid any searching process;2) our methods ensure no four or six cycles in the bipartite graphs corresponding to the LDPC codes;3) our methods are direct constructions of quasi-cyclic LDPC codes which do not use any other quasi-cyclic LDPC codes of small length like component codes or any other algorithms/cyclic codes like building block;4)the computations of the parameters involved are based on elementary number theory,thus very simple and fast.Simulation results show that the constructed regular codes of high rates perform almost 1.25 dB above Shannon limit and have no error floor down to the bit-error rate of 10-6.展开更多
The deformation performance index limits of high reinforced concrete （RC） shear wall components based on Chinese codes were discussed by the nonlinear finite element method. Two typical RC shear wall specimens in th...The deformation performance index limits of high reinforced concrete （RC） shear wall components based on Chinese codes were discussed by the nonlinear finite element method. Two typical RC shear wall specimens in the previous work were first used to verify the correctness of the nonlinear finite element method. Then, the nonlinear finite element method was applied to study the deformability of a set of high RC shear wall components designed according to current Chinese codes and with shear span ratio λ≥2.0. Parametric studies were made on the influence of shear span ratio, axial compression ratio, ratio of flexural capacity to shear capacity and main flexural reinforcement ratio of confined botmdary members. Finally, the deformation performance index and its limits of high RC shear wall components under severe earthquakes were proposed by the finite element model results, which offers a reference in determining the performance status of RC shear wall components designed based on Chinese codes.展开更多
The test vector compression is a key technique to reduce IC test time and cost since the explosion of the test data of system on chip （SoC） in recent years. To reduce the bandwidth requirement between the automatic ...The test vector compression is a key technique to reduce IC test time and cost since the explosion of the test data of system on chip （SoC） in recent years. To reduce the bandwidth requirement between the automatic test equipment （ATE） and the CUT （circuit under test） effectively, a novel VSPTIDR （variable shifting prefix-tail identifier reverse） code for test stimulus data compression is designed. The encoding scheme is defined and analyzed in detail, and the decoder is presented and discussed. While the probability of 0 bits in the test set is greater than 0.92, the compression ratio from VSPTIDR code is better than the frequency-directed run-length （FDR） code, which can be proved by theoretical analysis and experiments. And the on-chip area overhead of VSPTIDR decoder is about 15.75 % less than the FDR decoder.展开更多
文摘For limited distortion source coding, it is generally considered that the minimum value of the coding average distortion is 0, and the maximum value is the minimum distortion value of making R(D) = 0. This is the definition domain of the information rate distortion function. In this paper, the upper and lower bounds of the information rate distortion function R(D) are derived and computed for the typical sources. The results show that the lower bound of the coding average distortion D is related to the symbol distortion function, which can further improve the theory of limited distortion source coding.
文摘This paper presents a new test data compression/decompression method for SoC testing,called hybrid run length codes. The method makes a full analysis of the factors which influence test parameters：compression ratio,test application time, and area overhead. To improve the compression ratio, the new method is based on variable-to-variable run length codes,and a novel algorithm is proposed to reorder the test vectors and fill the unspecified bits in the pre-processing step. With a novel on-chip decoder, low test application time and low area overhead are obtained by hybrid run length codes. Finally, an experimental comparison on ISCAS 89 benchmark circuits validates the proposed method
基金supported by the National Natural Science Foundation of China under Grants No.61172085,No.61103221,No.61133014,No.11061130539 and No.61021004
文摘This paper is concerned with (3,n) and (4,n) regular quasi-cyclic Low Density Parity Check (LDPC) code constructions from elementary number theory.Given the column weight,we determine the shift values of the circulant permutation matrices via arithmetic analysis.The proposed constructions of quasi-cyclic LDPC codes achieve the following main advantages simultaneously:1) our methods are constructive in the sense that we avoid any searching process;2) our methods ensure no four or six cycles in the bipartite graphs corresponding to the LDPC codes;3) our methods are direct constructions of quasi-cyclic LDPC codes which do not use any other quasi-cyclic LDPC codes of small length like component codes or any other algorithms/cyclic codes like building block;4)the computations of the parameters involved are based on elementary number theory,thus very simple and fast.Simulation results show that the constructed regular codes of high rates perform almost 1.25 dB above Shannon limit and have no error floor down to the bit-error rate of 10-6.
基金Project(2009ZA04) supported by the Independent Research Foundation of State Key Laboratory of Subtropical Architecture Science,China
文摘The deformation performance index limits of high reinforced concrete （RC） shear wall components based on Chinese codes were discussed by the nonlinear finite element method. Two typical RC shear wall specimens in the previous work were first used to verify the correctness of the nonlinear finite element method. Then, the nonlinear finite element method was applied to study the deformability of a set of high RC shear wall components designed according to current Chinese codes and with shear span ratio λ≥2.0. Parametric studies were made on the influence of shear span ratio, axial compression ratio, ratio of flexural capacity to shear capacity and main flexural reinforcement ratio of confined botmdary members. Finally, the deformation performance index and its limits of high RC shear wall components under severe earthquakes were proposed by the finite element model results, which offers a reference in determining the performance status of RC shear wall components designed based on Chinese codes.
基金supported by the Shenzhen Government R&D Project under Grant No.JC200903160361A
文摘The test vector compression is a key technique to reduce IC test time and cost since the explosion of the test data of system on chip （SoC） in recent years. To reduce the bandwidth requirement between the automatic test equipment （ATE） and the CUT （circuit under test） effectively, a novel VSPTIDR （variable shifting prefix-tail identifier reverse） code for test stimulus data compression is designed. The encoding scheme is defined and analyzed in detail, and the decoder is presented and discussed. While the probability of 0 bits in the test set is greater than 0.92, the compression ratio from VSPTIDR code is better than the frequency-directed run-length （FDR） code, which can be proved by theoretical analysis and experiments. And the on-chip area overhead of VSPTIDR decoder is about 15.75 % less than the FDR decoder.
