The pattern run-length coding test data compression approach is extended by introducing don't care bit(x) propagation strategy into it.More than one core test sets for testing core-based System-on-Chip(SoC) are un...The pattern run-length coding test data compression approach is extended by introducing don't care bit(x) propagation strategy into it.More than one core test sets for testing core-based System-on-Chip(SoC) are unified into a single one,which is compressed by the extended coding technique.A reconfigurable scan test application mechanism is presented,in which test data for multiple cores are scanned and captured jointly to make SoC test application more efficient with low hardware overhead added.The proposed union test technique is applied to an academic SoC embedded by six large ISCAS'89 benchmarks,and to an ITC' 02 benchmark circuit.Experiment results show that compared with the existing schemes in which a core test set is compressed and applied independently of other cores,the proposed scheme can not only improve test data compression/decompression,but also reduce the redundant shift and capture cycles during scan testing,decreasing SoC test application time effectively.展开更多
The test vector compression is a key technique to reduce IC test time and cost since the explosion of the test data of system on chip （SoC） in recent years. To reduce the bandwidth requirement between the automatic ...The test vector compression is a key technique to reduce IC test time and cost since the explosion of the test data of system on chip （SoC） in recent years. To reduce the bandwidth requirement between the automatic test equipment （ATE） and the CUT （circuit under test） effectively, a novel VSPTIDR （variable shifting prefix-tail identifier reverse） code for test stimulus data compression is designed. The encoding scheme is defined and analyzed in detail, and the decoder is presented and discussed. While the probability of 0 bits in the test set is greater than 0.92, the compression ratio from VSPTIDR code is better than the frequency-directed run-length （FDR） code, which can be proved by theoretical analysis and experiments. And the on-chip area overhead of VSPTIDR decoder is about 15.75 % less than the FDR decoder.展开更多
基金Supported by the National Natural Science Fund of China (No.60876028)the key Project of Natural Science Foundation of the Anhui Higher Education Institutions (No.KJ2010A280)
文摘The pattern run-length coding test data compression approach is extended by introducing don't care bit(x) propagation strategy into it.More than one core test sets for testing core-based System-on-Chip(SoC) are unified into a single one,which is compressed by the extended coding technique.A reconfigurable scan test application mechanism is presented,in which test data for multiple cores are scanned and captured jointly to make SoC test application more efficient with low hardware overhead added.The proposed union test technique is applied to an academic SoC embedded by six large ISCAS'89 benchmarks,and to an ITC' 02 benchmark circuit.Experiment results show that compared with the existing schemes in which a core test set is compressed and applied independently of other cores,the proposed scheme can not only improve test data compression/decompression,but also reduce the redundant shift and capture cycles during scan testing,decreasing SoC test application time effectively.
基金supported by the Shenzhen Government R&D Project under Grant No.JC200903160361A
文摘The test vector compression is a key technique to reduce IC test time and cost since the explosion of the test data of system on chip （SoC） in recent years. To reduce the bandwidth requirement between the automatic test equipment （ATE） and the CUT （circuit under test） effectively, a novel VSPTIDR （variable shifting prefix-tail identifier reverse） code for test stimulus data compression is designed. The encoding scheme is defined and analyzed in detail, and the decoder is presented and discussed. While the probability of 0 bits in the test set is greater than 0.92, the compression ratio from VSPTIDR code is better than the frequency-directed run-length （FDR） code, which can be proved by theoretical analysis and experiments. And the on-chip area overhead of VSPTIDR decoder is about 15.75 % less than the FDR decoder.
