A major challenge in spatial transcriptomics(ST)is resolving cellular composition,especially in technologies lacking single-cell resolution.The mixture of transcriptional signals within spatial spots complicates decon...A major challenge in spatial transcriptomics(ST)is resolving cellular composition,especially in technologies lacking single-cell resolution.The mixture of transcriptional signals within spatial spots complicates deconvolution and downstream analyses.To uncover the spatial heterogeneity of tissues,we introduce SvdRFCTD,a reference-free spatial transcriptomics deconvolution method,which estimates the cell type proportions at each spot on the tissue.To fully capture the heterogeneity in the ST data,we combine SvdRFCTD with a Bayesian hierarchical negative binomial model with spatial effects incorporated in both the mean and dispersion of the gene expression,which is used to explicitly model the generative mechanism of cell type proportions.By integrating spatial information and leveraging marker gene information,SvdRFCTD accurately estimates cell type proportions and uncovers complex spatial patterns.We demonstrate the ability of SvdRFCTD to identify cell types on simulated datasets.By applying SvdRFCTD to mouse brain and human pancreatic ductal adenocarcinomas datasets,we observe significant cellular heterogeneity within the tissue sections and successfully identify regions with high proportions of aggregated cell types,along with the spatial relationships between different cell types.展开更多
A 10-bit 50-MS/s reference-free low power successive approximation register （SAR） analog-to-digital converter （ADC） is presented. An energy efficient switching scheme is utilized in this design to obtain low power...A 10-bit 50-MS/s reference-free low power successive approximation register （SAR） analog-to-digital converter （ADC） is presented. An energy efficient switching scheme is utilized in this design to obtain low power and high frequency operation performance without an additional analog power supply or on-chip/off-chip reference. An on-chip calibration DAC （CDAC） is implemented to cancel the offset of the latch-type sense amplifier （SA） to ensure precision whilst getting rid of the dependence on the pre-amplifier, so that the power consumption can be reduced further. The design was fabricated in IBM 0.18-μm 1P4M SOI CMOS process technology. At a 1.5-V supply and 50-MS/s with 5-MHz input, the ADC achieves an SNDR of 56.76 dB and consumes 1.72 mW, resulting in a figure of merit （FOM） of 61.1 fJ/conversion-step.展开更多
基金supported by the Natural Science Foundation of China[grant numbers 12201219,12271168,12171229]Natural Science Foundation of Shanghai[grant numbers 23JS1400500,23JS1400800,22ZR1420500].
文摘A major challenge in spatial transcriptomics(ST)is resolving cellular composition,especially in technologies lacking single-cell resolution.The mixture of transcriptional signals within spatial spots complicates deconvolution and downstream analyses.To uncover the spatial heterogeneity of tissues,we introduce SvdRFCTD,a reference-free spatial transcriptomics deconvolution method,which estimates the cell type proportions at each spot on the tissue.To fully capture the heterogeneity in the ST data,we combine SvdRFCTD with a Bayesian hierarchical negative binomial model with spatial effects incorporated in both the mean and dispersion of the gene expression,which is used to explicitly model the generative mechanism of cell type proportions.By integrating spatial information and leveraging marker gene information,SvdRFCTD accurately estimates cell type proportions and uncovers complex spatial patterns.We demonstrate the ability of SvdRFCTD to identify cell types on simulated datasets.By applying SvdRFCTD to mouse brain and human pancreatic ductal adenocarcinomas datasets,we observe significant cellular heterogeneity within the tissue sections and successfully identify regions with high proportions of aggregated cell types,along with the spatial relationships between different cell types.
文摘A 10-bit 50-MS/s reference-free low power successive approximation register （SAR） analog-to-digital converter （ADC） is presented. An energy efficient switching scheme is utilized in this design to obtain low power and high frequency operation performance without an additional analog power supply or on-chip/off-chip reference. An on-chip calibration DAC （CDAC） is implemented to cancel the offset of the latch-type sense amplifier （SA） to ensure precision whilst getting rid of the dependence on the pre-amplifier, so that the power consumption can be reduced further. The design was fabricated in IBM 0.18-μm 1P4M SOI CMOS process technology. At a 1.5-V supply and 50-MS/s with 5-MHz input, the ADC achieves an SNDR of 56.76 dB and consumes 1.72 mW, resulting in a figure of merit （FOM） of 61.1 fJ/conversion-step.
