Purpose The high-energy photon source(HEPS)has set higher-performance requirements for pixel readout chips.The conventional design method,analog-on-top,encounters considerable challenges when implementing pixel readou...Purpose The high-energy photon source(HEPS)has set higher-performance requirements for pixel readout chips.The conventional design method,analog-on-top,encounters considerable challenges when implementing pixel readout chips that include high-performance,large-scale,complex digital circuits.Consequently,it is essential to explore a new design method.Methods This paper proposes a new design method named digital-on-top,which takes digital circuit design as the top level.Based on CMOS 130 nm technology,a pixel readout chip named BP_V40S_DOT has been designed using this method.The chip contains an array of 128×96 pixels with a pixel size of 140μm×140μm,working in single-photon counting mode.Results Using the digital-on-top design method,the BP_V40S_DOT chip achieves serial readout with zero dead time at the system clock with a frequency up to 25 MHz,and the equivalent noise charge is 146 e-.It has implemented a new type of global clock-synchronized digital circuit architecture.Additionally,the new method significantly reduces the design cycle of the pixel readout chip and improves design efficiency.Conclusion In contrast to the conventional analog-on-top design method,the digital-on-top design method comprehensively accounts for the signal integrity and parasitic effects of the chip,enabling the rapid implementation of ultra-large-scale pixel readout chips with high-performance,complex digital circuits,thus better fulfilling the requirements of HEPS.展开更多
A high dynamic range readout system,consisting of a multi-dynode readout PMT and a VA32 chip,is presented.An LED system is set up to calibrate the relative gains between the dynodes,and the ADC counts per MIPs from dy...A high dynamic range readout system,consisting of a multi-dynode readout PMT and a VA32 chip,is presented.An LED system is set up to calibrate the relative gains between the dynodes,and the ADC counts per MIPs from dynode 7 are determined under cosmic-ray calibration.A dynamic range from 0.5 MIPs to 1×10 5 MIPs is achieved.展开更多
基金supported by the National Natural Science Foundation of China(No.22127901)the Scientific Instrument Developing Project of the Chinese Academy of Sciences(No.ZDKYYQ20200007)+1 种基金the National Talent Program-Young Top Talent,High Energy Photon Source(HEPS)—a major national science and technology infrastructure in Chinathe State Key Laboratory of Particle Detection and Electronics of China(Laboratory Code:2011DA173412).
文摘Purpose The high-energy photon source(HEPS)has set higher-performance requirements for pixel readout chips.The conventional design method,analog-on-top,encounters considerable challenges when implementing pixel readout chips that include high-performance,large-scale,complex digital circuits.Consequently,it is essential to explore a new design method.Methods This paper proposes a new design method named digital-on-top,which takes digital circuit design as the top level.Based on CMOS 130 nm technology,a pixel readout chip named BP_V40S_DOT has been designed using this method.The chip contains an array of 128×96 pixels with a pixel size of 140μm×140μm,working in single-photon counting mode.Results Using the digital-on-top design method,the BP_V40S_DOT chip achieves serial readout with zero dead time at the system clock with a frequency up to 25 MHz,and the equivalent noise charge is 146 e-.It has implemented a new type of global clock-synchronized digital circuit architecture.Additionally,the new method significantly reduces the design cycle of the pixel readout chip and improves design efficiency.Conclusion In contrast to the conventional analog-on-top design method,the digital-on-top design method comprehensively accounts for the signal integrity and parasitic effects of the chip,enabling the rapid implementation of ultra-large-scale pixel readout chips with high-performance,complex digital circuits,thus better fulfilling the requirements of HEPS.
基金Supported by Ministry of Science and Technology of China (2010CB833002)Innovative Program of Chinese Academy of Sciences (KJCX2-YW-T16)
文摘A high dynamic range readout system,consisting of a multi-dynode readout PMT and a VA32 chip,is presented.An LED system is set up to calibrate the relative gains between the dynodes,and the ADC counts per MIPs from dynode 7 are determined under cosmic-ray calibration.A dynamic range from 0.5 MIPs to 1×10 5 MIPs is achieved.
