HFRS(HIAF FRagment Separator) will be the radioactive secondary beam separation line on High-Intensity heavy-ion Accelerator Facility(HIAF) in China. Several TPC detectors, with high count rates, are planned for parti...HFRS(HIAF FRagment Separator) will be the radioactive secondary beam separation line on High-Intensity heavy-ion Accelerator Facility(HIAF) in China. Several TPC detectors, with high count rates, are planned for particle identification and beam monitoring at HFRS. This paper presents an event-driven internal memory and synchronous readout(EDIMS)prototype ASIC chip. The aim is to provide HFRS-TPC with high-precision time and charge measurements with high count rates and a large dynamic range. The first prototype EDIMS chip integrated 16 channels and is fabricated using a 0.18-μm CMOS process. Each channel consists of a charge-sensitive amplifier, fast shaper, slow shaper, peak detect-and-hold circuit, discriminator with time-walk compensation, analog memory, and FIFO. The token ring is used for clock-synchronous readout. The chip is taped and tested.展开更多
In this paper,we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit（ASIC） dedicated to CdZnTe detectors for a hard X-ray imager in spa...In this paper,we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit（ASIC） dedicated to CdZnTe detectors for a hard X-ray imager in space applications.The readout channel is comprised of a charge sensitive amplifier,a CR-RC shaping amplifier,an analog output buffer,a fast shaper,and a discriminator.An 8-channel prototype ASIC is designed and fabricated in TSMC 0.35-μm mixed-signal CMOS technology,the die size of the prototype chip is 2.2×2.2 mm^2.The input energy range is from 5 to 350 keV.For this 8-channel prototype ASIC,the measured electrical characteristics are as follows：the overall gain of the readout channel is 210 V/pC,the linearity error is less than 2%,the crosstalk is less than 0.36%,The equivalent noise charge of a typical channel is 52.9 e^- at zero farad plus 8.2 e^- per picofarad,and the power consumption is less than 2.4 mW/channel.Through the measurement together with a CdZnTe detector,the energy resolution is 5.9%at the 59.5-keV line under the irradiation of the radioactive source ^（241）Am.The radiation effect experiments show that the proposed ASIC can resist the total ionization dose（TID） irradiation of higher than200 krad（Si）.展开更多
A multi-channel front-end ASIC has been developed for a fast neutron spectrometer based on Gas Electron Multiplier （GEM）-Time Projection Chamber （TPC）. Charge Amplifier and Shaping Amplifier for GEM （CASAGEM） in...A multi-channel front-end ASIC has been developed for a fast neutron spectrometer based on Gas Electron Multiplier （GEM）-Time Projection Chamber （TPC）. Charge Amplifier and Shaping Amplifier for GEM （CASAGEM） integrates 16＋1 channels： 16 channels for anodes and 1 channel for cathode. The gain and the shaping time are adjustable from 2 to 40 mV/fC and from 20 to 80 ns, respectively. The prototype ASIC is fabricated in 0.35 μm CMOS process. An evaluation Print Circuit Board （PCB） was also developed for chip tests. In total 20 chips have been tested. The integrated nonlinearity is less than 1%. The equivalent noise electrons is less than 2000e when the input capacitor is 50 pF. The time jitter is less than 1 ns. The design and the test results are presented in the paper.展开更多
Integrated circuits of deep submicron(DSM) CMOS technology are advantageous in volume density, power consumption and thermal noise for multichannel particle detection systems,but there are challenges in the front-end ...Integrated circuits of deep submicron(DSM) CMOS technology are advantageous in volume density, power consumption and thermal noise for multichannel particle detection systems,but there are challenges in the front-end circuit design.In this paper,we present a 0.18μm CMOS front-end readout circuit for low noise CdZnTe detectors in tens of pF capacitance.Solutions to the noise and gate leak problems in DSM technologies are discussed in detail.A prototype chip was designed,with a charge sensitive preamplifier,a 4th order semi-Gaussian shaper and several output drivers.Test results show that the chip has an equivalent noise charge of 164 e,without connecting it to a detector,with an integral nonlinearity of<0.21%and differential nonlinearity of<3.75%.展开更多
A low-noise readout integrated circuit for high-energy particle detector is presented.The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration.Continuo...A low-noise readout integrated circuit for high-energy particle detector is presented.The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration.Continuous-time semi-Gaussian filter is chosen to avoid switch noise.The peaking time of pulse shaper and the gain can be programmed to satisfy multi-application.The readout integrated circuit has been designed and fabricated using a 0.35 μm double-poly triple-metal CMOS technology.Test results show the functions of the readout integrated circuit are correct.The equivalent noise charge with no detector connected is 500–700 e in the typical mode,the gain is tunable within 13–130 mV/fC and the peaking time varies from 0.7 to 1.6 μs,in which the average gain is about 20.5 mV/fC,and the linearity reaches 99.2%.展开更多
X射线探测器是X射线成像系统的关键部件之一,对成像质量具有决定性作用。然而,随着探测器像素尺寸微缩化、阵列规模指数级扩张,传统探测器面临数据传输带宽受限、功耗激增和信号延迟累积等挑战。因此,在探测器源端引入人工智能(AI)技术...X射线探测器是X射线成像系统的关键部件之一,对成像质量具有决定性作用。然而,随着探测器像素尺寸微缩化、阵列规模指数级扩张,传统探测器面临数据传输带宽受限、功耗激增和信号延迟累积等挑战。因此,在探测器源端引入人工智能(AI)技术成为必然趋势。基于此,系统综述面向智能X射线成像探测器的感算融合架构及实现技术最新进展。首先,剖析光子计数型读出专用集成电路(Application Specific Integrated Circuit,ASIC)在架构优化与能效提升方面的技术突破;其次,探讨通过模拟神经网络实现源端信号实时处理的感内计算技术路径;最后,从算法-电路协同设计角度分析存算一体技术在突破冯·诺依曼架构瓶颈中的创新实践,为构建高能效、低延迟的智能化X射线探测系统提供理论支撑与技术路线。展开更多
研制了一种适用于高能物理GEM探测器读出系统的数字芯片。芯片采用PAD读出方式,对GEM探测器的输出直接采样,对采样到的信号放大并成形,判断该输入是否超过由外部DAC设定的阈值,给出判断结果,并按照一个串行协议读出。芯片采用0.35μm/3....研制了一种适用于高能物理GEM探测器读出系统的数字芯片。芯片采用PAD读出方式,对GEM探测器的输出直接采样,对采样到的信号放大并成形,判断该输入是否超过由外部DAC设定的阈值,给出判断结果,并按照一个串行协议读出。芯片采用0.35μm/3.3 V CMOS工艺设计,后仿真结果显示芯片达到预期研制目标。展开更多
基金supported by the National Natural Science Foundation of China (Nos. 11975293 and 12105338)the Strategic Priority Research Program of Chinese Academy of Science (Nos. XDB 34040200 and XPB 23)the Technology Innovation Project of Instrument and Equipment Function Development of Chinese Academy of Sciences (No. 2023g102)。
文摘HFRS(HIAF FRagment Separator) will be the radioactive secondary beam separation line on High-Intensity heavy-ion Accelerator Facility(HIAF) in China. Several TPC detectors, with high count rates, are planned for particle identification and beam monitoring at HFRS. This paper presents an event-driven internal memory and synchronous readout(EDIMS)prototype ASIC chip. The aim is to provide HFRS-TPC with high-precision time and charge measurements with high count rates and a large dynamic range. The first prototype EDIMS chip integrated 16 channels and is fabricated using a 0.18-μm CMOS process. Each channel consists of a charge-sensitive amplifier, fast shaper, slow shaper, peak detect-and-hold circuit, discriminator with time-walk compensation, analog memory, and FIFO. The token ring is used for clock-synchronous readout. The chip is taped and tested.
基金supported by the National Key Scientific Instrument and Equipment Development Project(No.2011YQ040082)the National Natural Science Foundation of China(Nos.11475136,11575144,61176094)the Shaanxi Natural Science Foundation of China(No.2015JM1016)
文摘In this paper,we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit（ASIC） dedicated to CdZnTe detectors for a hard X-ray imager in space applications.The readout channel is comprised of a charge sensitive amplifier,a CR-RC shaping amplifier,an analog output buffer,a fast shaper,and a discriminator.An 8-channel prototype ASIC is designed and fabricated in TSMC 0.35-μm mixed-signal CMOS technology,the die size of the prototype chip is 2.2×2.2 mm^2.The input energy range is from 5 to 350 keV.For this 8-channel prototype ASIC,the measured electrical characteristics are as follows：the overall gain of the readout channel is 210 V/pC,the linearity error is less than 2%,the crosstalk is less than 0.36%,The equivalent noise charge of a typical channel is 52.9 e^- at zero farad plus 8.2 e^- per picofarad,and the power consumption is less than 2.4 mW/channel.Through the measurement together with a CdZnTe detector,the energy resolution is 5.9%at the 59.5-keV line under the irradiation of the radioactive source ^（241）Am.The radiation effect experiments show that the proposed ASIC can resist the total ionization dose（TID） irradiation of higher than200 krad（Si）.
基金Supported by National Natural Science Foundation of China(11275109)
文摘A multi-channel front-end ASIC has been developed for a fast neutron spectrometer based on Gas Electron Multiplier （GEM）-Time Projection Chamber （TPC）. Charge Amplifier and Shaping Amplifier for GEM （CASAGEM） integrates 16＋1 channels： 16 channels for anodes and 1 channel for cathode. The gain and the shaping time are adjustable from 2 to 40 mV/fC and from 20 to 80 ns, respectively. The prototype ASIC is fabricated in 0.35 μm CMOS process. An evaluation Print Circuit Board （PCB） was also developed for chip tests. In total 20 chips have been tested. The integrated nonlinearity is less than 1%. The equivalent noise electrons is less than 2000e when the input capacitor is 50 pF. The time jitter is less than 1 ns. The design and the test results are presented in the paper.
基金supported by the National Natural Science Foundation of China (No.61006021)
文摘Integrated circuits of deep submicron(DSM) CMOS technology are advantageous in volume density, power consumption and thermal noise for multichannel particle detection systems,but there are challenges in the front-end circuit design.In this paper,we present a 0.18μm CMOS front-end readout circuit for low noise CdZnTe detectors in tens of pF capacitance.Solutions to the noise and gate leak problems in DSM technologies are discussed in detail.A prototype chip was designed,with a charge sensitive preamplifier,a 4th order semi-Gaussian shaper and several output drivers.Test results show that the chip has an equivalent noise charge of 164 e,without connecting it to a detector,with an integral nonlinearity of<0.21%and differential nonlinearity of<3.75%.
基金Supported by the National Natural Science Foundation of China (No.40704025)
文摘A low-noise readout integrated circuit for high-energy particle detector is presented.The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration.Continuous-time semi-Gaussian filter is chosen to avoid switch noise.The peaking time of pulse shaper and the gain can be programmed to satisfy multi-application.The readout integrated circuit has been designed and fabricated using a 0.35 μm double-poly triple-metal CMOS technology.Test results show the functions of the readout integrated circuit are correct.The equivalent noise charge with no detector connected is 500–700 e in the typical mode,the gain is tunable within 13–130 mV/fC and the peaking time varies from 0.7 to 1.6 μs,in which the average gain is about 20.5 mV/fC,and the linearity reaches 99.2%.
文摘X射线探测器是X射线成像系统的关键部件之一,对成像质量具有决定性作用。然而,随着探测器像素尺寸微缩化、阵列规模指数级扩张,传统探测器面临数据传输带宽受限、功耗激增和信号延迟累积等挑战。因此,在探测器源端引入人工智能(AI)技术成为必然趋势。基于此,系统综述面向智能X射线成像探测器的感算融合架构及实现技术最新进展。首先,剖析光子计数型读出专用集成电路(Application Specific Integrated Circuit,ASIC)在架构优化与能效提升方面的技术突破;其次,探讨通过模拟神经网络实现源端信号实时处理的感内计算技术路径;最后,从算法-电路协同设计角度分析存算一体技术在突破冯·诺依曼架构瓶颈中的创新实践,为构建高能效、低延迟的智能化X射线探测系统提供理论支撑与技术路线。
文摘研制了一种适用于高能物理GEM探测器读出系统的数字芯片。芯片采用PAD读出方式,对GEM探测器的输出直接采样,对采样到的信号放大并成形,判断该输入是否超过由外部DAC设定的阈值,给出判断结果,并按照一个串行协议读出。芯片采用0.35μm/3.3 V CMOS工艺设计,后仿真结果显示芯片达到预期研制目标。
