In this data explosion era,ensuring the secure storage,access,and transmission of information is imperative,encom-passing all aspects ranging from safeguarding personal devices to formulating national information secu...In this data explosion era,ensuring the secure storage,access,and transmission of information is imperative,encom-passing all aspects ranging from safeguarding personal devices to formulating national information security strategies.Leverag-ing the potential offered by dual-type carriers for transportation and employing optical modulation techniques to develop high reconfigurable ambipolar optoelectronic transistors enables effective implementation of information destruction after read-ing,thereby guaranteeing data security.In this study,a reconfigurable ambipolar optoelectronic synaptic transistor based on poly(3-hexylthiophene)(P3HT)and poly[[N,N-bis(2-octyldodecyl)-napthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,5′-(2,2′-bithiophene)](N2200)blend film was fabricated through solution-processed method.The resulting transistor exhib-ited a relatively large ON/OFF ratio of 10^(3) in both n-and p-type regions,and tunable photoconductivity after light illumination,particularly with green light.The photo-generated carriers could be effectively trapped under the gate bias,indicating its poten-tial application in mimicking synaptic behaviors.Furthermore,the synaptic plasticity,including volatile/non-volatile and excita-tory/inhibitory characteristics,could be finely modulated by electrical and optical stimuli.These optoelectronic reconfigurable properties enable the realization of information light assisted burn after reading.This study not only offers valuable insights for the advancement of high-performance ambipolar organic optoelectronic synaptic transistors but also presents innovative ideas for the future information security access systems.展开更多
This paper presents a new dual V_t 8 T SRAM cell having single bit-line read and write, in addition to Write Assist and Read Isolation（WARI）. Also a faster write back scheme is proposed for the half selected cells. ...This paper presents a new dual V_t 8 T SRAM cell having single bit-line read and write, in addition to Write Assist and Read Isolation（WARI）. Also a faster write back scheme is proposed for the half selected cells. A high V_t device is used for interrupting the supply to one of the inverters for weakening the feedback loop for assisted write. The proposed cell provides an improved read static noise margin（RSNM） due to the bit-line isolation during the read. Static noise margins for data read（RSNM）, write（WSNM）, read delay, write delay, data retention voltage（DRV）, leakage and average powers have been calculated. The proposed cell was found to operate properly at a supply voltage as small as 0.41 V. A new write back scheme has been suggested for half-selected cells,which uses a single NMOS access device and provides reduced delay, pulse timing hardware requirements and power consumption. The proposed new WARI 8 T cell shows better performance in terms of easier write, improved read noise margin, reduced leakage power, and less delay as compared to the existing schemes that have been available so far. It was also observed that with proper adjustment of the cell ratio the supply voltage can further be reduced to 0.2 V.展开更多
基金the National Natural-Science Foundation of China(Grant No.62304137)Guangdong Basic and Applied Basic Research Foundation(Grant Nos.2023A1515012479,2024A1515011737,and 2024A1515010006)+4 种基金the Science and Technology Innovation Commission of Shenzhen(Grant No.JCYJ20220818100206013)RSC Researcher Collaborations Grant(Grant No.C23-2422436283)State Key Laboratory of Radio Frequency Heterogeneous Integration(Independent Scientific Research Program No.2024010)the Project on Frontier and Interdisciplinary Research Assessment,Academic Divisions of the Chinese Academy of Sciences(Grant No.XK2023XXA002)NTUT-SZU Joint Research Program.
文摘In this data explosion era,ensuring the secure storage,access,and transmission of information is imperative,encom-passing all aspects ranging from safeguarding personal devices to formulating national information security strategies.Leverag-ing the potential offered by dual-type carriers for transportation and employing optical modulation techniques to develop high reconfigurable ambipolar optoelectronic transistors enables effective implementation of information destruction after read-ing,thereby guaranteeing data security.In this study,a reconfigurable ambipolar optoelectronic synaptic transistor based on poly(3-hexylthiophene)(P3HT)and poly[[N,N-bis(2-octyldodecyl)-napthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,5′-(2,2′-bithiophene)](N2200)blend film was fabricated through solution-processed method.The resulting transistor exhib-ited a relatively large ON/OFF ratio of 10^(3) in both n-and p-type regions,and tunable photoconductivity after light illumination,particularly with green light.The photo-generated carriers could be effectively trapped under the gate bias,indicating its poten-tial application in mimicking synaptic behaviors.Furthermore,the synaptic plasticity,including volatile/non-volatile and excita-tory/inhibitory characteristics,could be finely modulated by electrical and optical stimuli.These optoelectronic reconfigurable properties enable the realization of information light assisted burn after reading.This study not only offers valuable insights for the advancement of high-performance ambipolar organic optoelectronic synaptic transistors but also presents innovative ideas for the future information security access systems.
文摘This paper presents a new dual V_t 8 T SRAM cell having single bit-line read and write, in addition to Write Assist and Read Isolation（WARI）. Also a faster write back scheme is proposed for the half selected cells. A high V_t device is used for interrupting the supply to one of the inverters for weakening the feedback loop for assisted write. The proposed cell provides an improved read static noise margin（RSNM） due to the bit-line isolation during the read. Static noise margins for data read（RSNM）, write（WSNM）, read delay, write delay, data retention voltage（DRV）, leakage and average powers have been calculated. The proposed cell was found to operate properly at a supply voltage as small as 0.41 V. A new write back scheme has been suggested for half-selected cells,which uses a single NMOS access device and provides reduced delay, pulse timing hardware requirements and power consumption. The proposed new WARI 8 T cell shows better performance in terms of easier write, improved read noise margin, reduced leakage power, and less delay as compared to the existing schemes that have been available so far. It was also observed that with proper adjustment of the cell ratio the supply voltage can further be reduced to 0.2 V.
