The advantages of read-only storage is the predominance of optical recording relative to magnetic and other rewritable methods. Multilevel （ML） read-only technology has been a trend to improve the data capacity and ...The advantages of read-only storage is the predominance of optical recording relative to magnetic and other rewritable methods. Multilevel （ML） read-only technology has been a trend to improve the data capacity and transfer rate. Based on the principle and coding method of ML, this paper demonstrates some ML read-only recording methods, of which a new ML read-only recording is developed. This recording method integrates amplitude modulation achieved by the reaction mechanism of physics and chemistry of photoresist with the run-length-limited technology. The discs can be achieved using standard photoresist mastering and replication techniques with great compatibility to conventional binary read-only discs.展开更多
A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:...A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:positive pumping voltage(VPP=4.75 V) ,negative pumping voltage(VNN=4.75 V) ,and VNNL(=VNN/2) generation circuit were proposed.In addition,switching powers CG high voltage(CG_HV) ,CG low voltage(CG_LV) ,TG high voltage(TG_HV) ,TG low voltage(TG_LV) ,VNNL_CG and VNNL_TG switching circuit were supplied for the CG and TG driving circuit.Furthermore,a sequential pumping scheme and a new ring oscillator with a dual oscillation period were proposed.To reduce a power consumption of EEPROM in the write mode,the reference voltages VREF_VPP for VPP and VREE_VNN for VNN were used by dividing VDD(1.2 V) supply voltage supplied from the analog block in stead of removing the reference voltage generators.A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was proposed.The result shows that the power dissipation is 0.34μW in the read mode,13.76μW in the program mode,and 13.66μW in the erase mode.展开更多
In this work,a novel one-time-programmable memory unit based on a Schottky-type p-GaN diode is proposed.During the programming process,the junction switches from a high-resistance state to a low-resistance state throu...In this work,a novel one-time-programmable memory unit based on a Schottky-type p-GaN diode is proposed.During the programming process,the junction switches from a high-resistance state to a low-resistance state through Schottky junction breakdown,and the state is permanently preserved.The memory unit features a current ratio of more than 10^(3),a read voltage window of 6 V,a programming time of less than 10^(−4)s,a stability of more than 108 read cycles,and a lifetime of far more than 10 years.Besides,the fabrication of the device is fully compatible with commercial Si-based GaN process platforms,which is of great significance for the realization of low-cost read-only memory in all-GaN integration.展开更多
A method was developed to estimate EEPROM device life based on the consistency for break- down charge, QBD, for constant voltage time dependent dielectric breakdown （TDDB） and constant current TDDB stress tests. Alt...A method was developed to estimate EEPROM device life based on the consistency for break- down charge, QBD, for constant voltage time dependent dielectric breakdown （TDDB） and constant current TDDB stress tests. Although an EEPROM works with a constant voltage, QBD for the tunnel oxide can be extracted using a constant current TDDB. Once the charge through the tunnel oxide, △QFG, is measured, the lower limit of the EEPROM life can be related to QBD/△QFG. The method is reached by erase/write cycle tests on an EEPROM.展开更多
This paper presents a novel direct digital frequency synthesizer （DDFS） architecture based on nonlinear DAC coarse quantization and the ROM-based piecewise approximation method, which has the advantages of high spee...This paper presents a novel direct digital frequency synthesizer （DDFS） architecture based on nonlinear DAC coarse quantization and the ROM-based piecewise approximation method, which has the advantages of high speed, low power and low hardware resources. By subdividing the sinusoid into a collection of phase segments, the same initial value of each segment is realized by a nonlinear DAC. The ROM is decomposed with a coarse ROM and fine ROM using the piecewise approximation method. Then, the coarse ROM stores the offsets between the initial value of the common segment and the initial value of each line in the same segment. Meanwhile, the fine ROM stores the differences between the line values and the initial value of each line. A ROM compression ratio of 32 can be achieved in the case of 11 bit phase and 9 bit amplitude. Based on the above method, a prototype chip was fabricated using 1.4 #m GaAs HBT technology. The measurement shows an average spurious-free dynamic range （SFDR） of 45 dBc, with the worst SFDR only 40.07 dBc at a 4.0 GHz clock. The chip area is 4.6 × 3.7 mm2 and it consumes 7 W from a --4.9 V power supply.展开更多
基金Project supported by the National Natural Science Foundation of China （Grant No 60577035）.
文摘The advantages of read-only storage is the predominance of optical recording relative to magnetic and other rewritable methods. Multilevel （ML） read-only technology has been a trend to improve the data capacity and transfer rate. Based on the principle and coding method of ML, this paper demonstrates some ML read-only recording methods, of which a new ML read-only recording is developed. This recording method integrates amplitude modulation achieved by the reaction mechanism of physics and chemistry of photoresist with the run-length-limited technology. The discs can be achieved using standard photoresist mastering and replication techniques with great compatibility to conventional binary read-only discs.
基金Project supported by the Second Stage of Brain Korea 21
文摘A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:positive pumping voltage(VPP=4.75 V) ,negative pumping voltage(VNN=4.75 V) ,and VNNL(=VNN/2) generation circuit were proposed.In addition,switching powers CG high voltage(CG_HV) ,CG low voltage(CG_LV) ,TG high voltage(TG_HV) ,TG low voltage(TG_LV) ,VNNL_CG and VNNL_TG switching circuit were supplied for the CG and TG driving circuit.Furthermore,a sequential pumping scheme and a new ring oscillator with a dual oscillation period were proposed.To reduce a power consumption of EEPROM in the write mode,the reference voltages VREF_VPP for VPP and VREE_VNN for VNN were used by dividing VDD(1.2 V) supply voltage supplied from the analog block in stead of removing the reference voltage generators.A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was proposed.The result shows that the power dissipation is 0.34μW in the read mode,13.76μW in the program mode,and 13.66μW in the erase mode.
基金supported in part by the National Key Research and Development Program of China under Grant 2022YFB3604400in part by the Youth Innovation Promotion Association of Chinese Academy Sciences (CAS)+4 种基金in part by the CAS-Croucher Funding Scheme under Grant CAS22801in part by National Natural Science Foundation of China under Grant 62334012, Grant 62074161, Grant 62004213, Grant U20A20208, and Grant 62304252in part by the Beijing Municipal Science and Technology Commission project under Grant Z201100008420009 and Grant Z211100007921018in part by the University of CASin part by the IMECAS-HKUST-Joint Laboratory of Microelectronics
文摘In this work,a novel one-time-programmable memory unit based on a Schottky-type p-GaN diode is proposed.During the programming process,the junction switches from a high-resistance state to a low-resistance state through Schottky junction breakdown,and the state is permanently preserved.The memory unit features a current ratio of more than 10^(3),a read voltage window of 6 V,a programming time of less than 10^(−4)s,a stability of more than 108 read cycles,and a lifetime of far more than 10 years.Besides,the fabrication of the device is fully compatible with commercial Si-based GaN process platforms,which is of great significance for the realization of low-cost read-only memory in all-GaN integration.
基金Supported the State Important Sci-Tech Special Projects(2009ZX02306-04)
文摘A method was developed to estimate EEPROM device life based on the consistency for break- down charge, QBD, for constant voltage time dependent dielectric breakdown （TDDB） and constant current TDDB stress tests. Although an EEPROM works with a constant voltage, QBD for the tunnel oxide can be extracted using a constant current TDDB. Once the charge through the tunnel oxide, △QFG, is measured, the lower limit of the EEPROM life can be related to QBD/△QFG. The method is reached by erase/write cycle tests on an EEPROM.
基金supported by the National Basic Research Program of China(No.2010CB327505)
文摘This paper presents a novel direct digital frequency synthesizer （DDFS） architecture based on nonlinear DAC coarse quantization and the ROM-based piecewise approximation method, which has the advantages of high speed, low power and low hardware resources. By subdividing the sinusoid into a collection of phase segments, the same initial value of each segment is realized by a nonlinear DAC. The ROM is decomposed with a coarse ROM and fine ROM using the piecewise approximation method. Then, the coarse ROM stores the offsets between the initial value of the common segment and the initial value of each line in the same segment. Meanwhile, the fine ROM stores the differences between the line values and the initial value of each line. A ROM compression ratio of 32 can be achieved in the case of 11 bit phase and 9 bit amplitude. Based on the above method, a prototype chip was fabricated using 1.4 #m GaAs HBT technology. The measurement shows an average spurious-free dynamic range （SFDR） of 45 dBc, with the worst SFDR only 40.07 dBc at a 4.0 GHz clock. The chip area is 4.6 × 3.7 mm2 and it consumes 7 W from a --4.9 V power supply.
