The high working junction temperature of power component is the most common reason of its failure. So the thermal design is of vital importance in electronic control unit （ECU） design. By means of circuit simulation...The high working junction temperature of power component is the most common reason of its failure. So the thermal design is of vital importance in electronic control unit （ECU） design. By means of circuit simulation, the thermal design of ECU for electronic unit pump （EUP） fuel system is applied. The power dissipation model of each power component in the ECU is created and simulated. According to the analyses of simulation results, the factors which affect the power dissipation of components are analyzed. Then the ways for reducing the power dissipation of power components are carried out. The power dissipation of power components at different engine state is calculated and analyzed. The maximal power dissipation of each power component in all possible engine state is also carried out based on these simulations. A cooling system is designed based on these studies. The tests show that the maximum total power dissipation of ECU drops from 43.2 W to 33.84 W after these simulations and optimizations. These applications of simulations in thermal design of ECU can greatly increase the quality of the design, save the design cost and shorten design time展开更多
A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk o...A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumpingstage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications.展开更多
This paper presents a low power and high efficiency high voltage generator circuit embedded in electrically erasable programmable read-only memory（EEPROM）.The low power is minimized by a capacitance divider circuit ...This paper presents a low power and high efficiency high voltage generator circuit embedded in electrically erasable programmable read-only memory（EEPROM）.The low power is minimized by a capacitance divider circuit and a regulator circuit using the controlling clock switch technique.The high efficiency is dependent on the zero threshold voltage（V_（th）） MOSFET and the charge transfer switch（CTS） charge pump.The proposed high voltage generator circuit has been implemented in a 0.35μm EEPROM CMOS process.Measured results show that the proposed high voltage generator circuit has a low power consumption of about 150.48μW and a higher pumping efficiency（83.3%） than previously reported circuits.This high voltage generator circuit can also be widely used in low-power flash devices due to its high efficiency and low power dissipation.展开更多
A charge pump design is presented to operate at 10 kHz with 100 μA in a liquid crystal display (LCD) driver for cell phone. Optimal channel widths are designed by estimating the power consumption of the Fibonacci-lik...A charge pump design is presented to operate at 10 kHz with 100 μA in a liquid crystal display (LCD) driver for cell phone. Optimal channel widths are designed by estimating the power consumption of the Fibonacci-like charge pump. An optimal frequency is a compromise between the rise time and the dynamic power dissipation. The optimization of the two-phase nonoverlapping clock generator circuit improves the efficiency. Simulation results based on 1.2 μm complementary metal-oxide-semiconductor (CMOS) technology parameters verify the efficiency of the design.展开更多
For 3D vertical NAND flash memory, the charge pump output load is much larger than that of the planar NAND, resulting in the performance degradation of the conventional Dickson charge pump. Therefore, a novel all PMOS...For 3D vertical NAND flash memory, the charge pump output load is much larger than that of the planar NAND, resulting in the performance degradation of the conventional Dickson charge pump. Therefore, a novel all PMOS charge pump with high voltage boosting efficiency, large driving capability and high power efficiency for 3D V-NAND has been proposed. In this circuit, the Pellieoni structure is used to enhance the driving capability, two auxiliary substrate bias PMOS transistors are added to mitigate the body effect, and the degradation of the output voltage and boost efficiency caused by the threshold voltage drop is eliminated by dynamic gate control structure. Simulated results show that the proposed charge pump circuit can achieve the maximum boost efficiency of 86% and power efficiency of 50%. The output voltage of the proposed 9 stages charge pump can exceed 2 V under 2 MHz clock frequency in 2X nm 3D V-NAND technology. Our results provide guidance for the peripheral circuit design of high density 3D V-NAND integration.展开更多
文摘The high working junction temperature of power component is the most common reason of its failure. So the thermal design is of vital importance in electronic control unit （ECU） design. By means of circuit simulation, the thermal design of ECU for electronic unit pump （EUP） fuel system is applied. The power dissipation model of each power component in the ECU is created and simulated. According to the analyses of simulation results, the factors which affect the power dissipation of components are analyzed. Then the ways for reducing the power dissipation of power components are carried out. The power dissipation of power components at different engine state is calculated and analyzed. The maximal power dissipation of each power component in all possible engine state is also carried out based on these simulations. A cooling system is designed based on these studies. The tests show that the maximum total power dissipation of ECU drops from 43.2 W to 33.84 W after these simulations and optimizations. These applications of simulations in thermal design of ECU can greatly increase the quality of the design, save the design cost and shorten design time
基金supported by the Chinese National High-Tech Research and Development Program(No.2006AA04A108)the National Natural Science Foundation of China(No.2008AA010703).
文摘A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumpingstage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications.
基金supported by the National Natural Science Foundation of China(No.61072010)
文摘This paper presents a low power and high efficiency high voltage generator circuit embedded in electrically erasable programmable read-only memory（EEPROM）.The low power is minimized by a capacitance divider circuit and a regulator circuit using the controlling clock switch technique.The high efficiency is dependent on the zero threshold voltage（V_（th）） MOSFET and the charge transfer switch（CTS） charge pump.The proposed high voltage generator circuit has been implemented in a 0.35μm EEPROM CMOS process.Measured results show that the proposed high voltage generator circuit has a low power consumption of about 150.48μW and a higher pumping efficiency（83.3%） than previously reported circuits.This high voltage generator circuit can also be widely used in low-power flash devices due to its high efficiency and low power dissipation.
文摘A charge pump design is presented to operate at 10 kHz with 100 μA in a liquid crystal display (LCD) driver for cell phone. Optimal channel widths are designed by estimating the power consumption of the Fibonacci-like charge pump. An optimal frequency is a compromise between the rise time and the dynamic power dissipation. The optimization of the two-phase nonoverlapping clock generator circuit improves the efficiency. Simulation results based on 1.2 μm complementary metal-oxide-semiconductor (CMOS) technology parameters verify the efficiency of the design.
文摘For 3D vertical NAND flash memory, the charge pump output load is much larger than that of the planar NAND, resulting in the performance degradation of the conventional Dickson charge pump. Therefore, a novel all PMOS charge pump with high voltage boosting efficiency, large driving capability and high power efficiency for 3D V-NAND has been proposed. In this circuit, the Pellieoni structure is used to enhance the driving capability, two auxiliary substrate bias PMOS transistors are added to mitigate the body effect, and the degradation of the output voltage and boost efficiency caused by the threshold voltage drop is eliminated by dynamic gate control structure. Simulated results show that the proposed charge pump circuit can achieve the maximum boost efficiency of 86% and power efficiency of 50%. The output voltage of the proposed 9 stages charge pump can exceed 2 V under 2 MHz clock frequency in 2X nm 3D V-NAND technology. Our results provide guidance for the peripheral circuit design of high density 3D V-NAND integration.
