This work presents an implementation of an innovative single phase multilevel inverter using capacitors with reduced switches. The proposed Capacitor pattern H-bridge Multilevel Inverter (CPHMLI) topology consists of ...This work presents an implementation of an innovative single phase multilevel inverter using capacitors with reduced switches. The proposed Capacitor pattern H-bridge Multilevel Inverter (CPHMLI) topology consists of a proper number of Capacitor connected with switches and power sources. The advanced switching control supplied by Pulse Width Modulation (PDPWM) to attain mixed staircase switching state. The charging and discharging mode are achieved by calculating the voltage error at the load. Furthermore, to accomplish the higher voltage levels at the output with less number of semiconductors switches and simple commutation designed using CPHMLI topology. To prove the performance and effectiveness of the proposed approach, a set of experiments performed under various load conditions using MATLAB tool.展开更多
This paper proposes a zer o current and zero voltage switching (ZCZVS) PWM Boost full bridge (FB) conve rter. With series inductors, the leading switches can realize zero current swit ching (ZCS) in a wide load ra...This paper proposes a zer o current and zero voltage switching (ZCZVS) PWM Boost full bridge (FB) conve rter. With series inductors, the leading switches can realize zero current swit ching (ZCS) in a wide load range using the energy of the output capacitor. Ma king use of parasitic capacitors of the lagging switches and parallel auxiliary i nductance with the primary winding of the transformer, the lagging switches can realize zero voltage switching (ZVS) under any load. Compared with the ZCS PWM Boost FB converter, the new converter has no current duty cycle loss. Operat ional principle and parameter design are analyzed. Experimental results verify the effectiveness of the proposed converter.展开更多
文摘This work presents an implementation of an innovative single phase multilevel inverter using capacitors with reduced switches. The proposed Capacitor pattern H-bridge Multilevel Inverter (CPHMLI) topology consists of a proper number of Capacitor connected with switches and power sources. The advanced switching control supplied by Pulse Width Modulation (PDPWM) to attain mixed staircase switching state. The charging and discharging mode are achieved by calculating the voltage error at the load. Furthermore, to accomplish the higher voltage levels at the output with less number of semiconductors switches and simple commutation designed using CPHMLI topology. To prove the performance and effectiveness of the proposed approach, a set of experiments performed under various load conditions using MATLAB tool.
文摘This paper proposes a zer o current and zero voltage switching (ZCZVS) PWM Boost full bridge (FB) conve rter. With series inductors, the leading switches can realize zero current swit ching (ZCS) in a wide load range using the energy of the output capacitor. Ma king use of parasitic capacitors of the lagging switches and parallel auxiliary i nductance with the primary winding of the transformer, the lagging switches can realize zero voltage switching (ZVS) under any load. Compared with the ZCS PWM Boost FB converter, the new converter has no current duty cycle loss. Operat ional principle and parameter design are analyzed. Experimental results verify the effectiveness of the proposed converter.
