This paper presents a smart compensation system based on MCA7707 (a kind of signal processor). The li near errors and high order errors of a sensor (especially piezoresistive sensor) can be corrected by using this s...This paper presents a smart compensation system based on MCA7707 (a kind of signal processor). The li near errors and high order errors of a sensor (especially piezoresistive sensor) can be corrected by using this system. It can optimize the process of piezoresi stive sensor calibration and compensation, then, a total error factor within 0.2 % of the sensor′s repeatability errors is obtained. Data are recorded and coeff icients are determined automatically by this system, thus, the sensor compensati on is simplified greatly. For operating easily, a wizard compensation program is designed to correct every error and to get the optimum compensation.展开更多
Java technology is spreading rapidly all over the world in recent years. It is a popular application development language for its well-encapsulation, platform-independent and high security. There are great amounts of ...Java technology is spreading rapidly all over the world in recent years. It is a popular application development language for its well-encapsulation, platform-independent and high security. There are great amounts of Java games and other gadgets on mobile platforms, as well as on set-up-box systems. As Java applications become more sophisticated, the Java Virtual Machine (JVM) mid-dle-wares in embedded systems are not satisfying, Java-specific chips extend in the market. All existing Java-based system software or Operating System (OS) are used on JVM, they cannot be used on Java processors. It is important to develop a pure Java system software or OS so that embedded systems using Java processors will have great performance in Java applications. This paper presents a set of system software designed for a Java-specified processor VP6K, which is also a System-on-Chip (SoC). This system software includes real-time multitask dispatching, file management, device management, hardware drivers, and infrastructural Application Programming Interface (APIs). According to ex-perimental results, the system software provides interfaces for Java programs to fully handle CPU resource, so that all applications can be executed properly and efficiently. VP6K embedded platform shows its good performance for Java applications when the system software is implemented.展开更多
A fuzzy logic intelligent control system of pulsed MAG welding inverter based on digital signal processor(DSP)is proposed to obtain the consistency of arc length in pulsed MAG welding.The proposed control system combi...A fuzzy logic intelligent control system of pulsed MAG welding inverter based on digital signal processor(DSP)is proposed to obtain the consistency of arc length in pulsed MAG welding.The proposed control system combines the merits of intelligent control with DSP digital control.The fuzzy logic intelligent control system designed is a typical two-input-single-output structure,and regards the error and the change in error of peak arc voltage as two inputs and the background time as single output.The fuzzy logic intelligent control system is realized in a look-up table(LUT)method by using MATLAB based fuzzy logic toolbox,and the implement of LUT method based on DSP is also discussed.The pulsed MAG welding experimental results demonstrate that the developed fuzzy logic intelligent control system based on DSP has strong arc length controlling ability to accomplish the stable pulsed MAG welding process and controls pulsed MAG welding inverter digitally and intelligently.展开更多
A team of researchers from the University of Science and Technology of China(USTC)of the Chinese Academy of Sciences(CAS)and its partners have made significant advancements in random quantum circuit sampling with Zuch...A team of researchers from the University of Science and Technology of China(USTC)of the Chinese Academy of Sciences(CAS)and its partners have made significant advancements in random quantum circuit sampling with Zuchongzhi-3,a superconducting quantum computing prototype featuring 105 qubits and 182 couplers.展开更多
目前,多核实时系统中同步任务的节能调度研究主要针对的是同构多核处理器平台,而异构多核处理器架构能够更有效地发挥系统性能。将现有的研究直接应用于异构多核系统,在保证可调度性的情况下会导致能耗变高。对此,通过使用动态电压与频...目前,多核实时系统中同步任务的节能调度研究主要针对的是同构多核处理器平台,而异构多核处理器架构能够更有效地发挥系统性能。将现有的研究直接应用于异构多核系统,在保证可调度性的情况下会导致能耗变高。对此,通过使用动态电压与频率调节(Dynamic Voltage Frequency Scaling,DVFS)技术,研究异构多核实时系统中基于任务同步的节能调度问题,提出同步感知的最大能耗节省优先算法(Synchronization Aware-Largest Energy Saved First,SA-LESF)。该算法针对所有任务的速度配置进行迭代优化,直至所有任务均达到其最大限度节能的速度配置。此外,进一步提出基于动态松弛时间回收的同步感知最大能耗节省优先算法(Synchronization Aware-Largest Energy Saved First with Dynamic Reclamation,SA-LESF-DR)。该算法在保证实时任务可调度的同时,实施相应的回收策略,进一步降低系统能耗。实验结果表明,SA-LESF与SA-LESF-DR算法在能耗表现上具有优势,在相同任务集下,相比其他算法可节省高达30%的能耗。展开更多
This paper proposes a cochlear prosthetic system with an implanted digital signal processor （DSP）. This system transmits voice-band signals with a low data rate through the wireless link, free of the data-rate limit...This paper proposes a cochlear prosthetic system with an implanted digital signal processor （DSP）. This system transmits voice-band signals with a low data rate through the wireless link, free of the data-rate limitation and suitable for future development. By optimizing the speech processing algorithm and the DSP hardware design, the implanted DSP manages to execute the continuous interleaved sampling （CIS） algorithm at a clock frequency of 3MHz and a power consumption of only 1.91mW. With an analytic power-transmission efficiency of the wireless inductive link （40%）, the power overhead caused by the implanted DSP is derived as 2.87roW,which is trivial when compared with the power consumption of existing cochlear prosthetic systems （tens of milliwatts）. With the DSP implanted,this new system can.be easily developed into a fully implanted cochlear prosthesis.展开更多
Considering that the noises resulting from low modulation frequency are serious and cannot be totally eliminated by the classic filters,a novel infrared(IR) gas concentration detection system based on the least square...Considering that the noises resulting from low modulation frequency are serious and cannot be totally eliminated by the classic filters,a novel infrared(IR) gas concentration detection system based on the least square fast transverse filtering(LS-FTF) self-adaptive modern filter structure is proposed.The principle,procedure and simulation on the LS-FTF algorithm are described.The system schematic diagram and key techniques are discussed.The procedures for the ARM7 processor,including LS-FTF and main program,are demonstrated.Comparisons between the experimental results of the detection system using the LS-FTF algorithm and those of the system without using this algorithm are performed.By using the LS-FTF algorithm,the maximum detection error is decreased from 14.3 to 5.4,and also the detection stability increases as the variation range of the relative error becomes much smaller.The proposed LS-FTF self-adaptive denoising method can be of practical value for mid-IR gas detection,especially for weak signal detection.展开更多
As an important branch of information security algorithms,the efficient and flexible implementation of stream ciphers is vital.Existing implementation methods,such as FPGA,GPP and ASIC,provide a good support,but they ...As an important branch of information security algorithms,the efficient and flexible implementation of stream ciphers is vital.Existing implementation methods,such as FPGA,GPP and ASIC,provide a good support,but they could not achieve a better tradeoff between high speed processing and high flexibility.ASIC has fast processing speed,but its flexibility is poor,GPP has high flexibility,but the processing speed is slow,FPGA has high flexibility and processing speed,but the resource utilization is very low.This paper studies a stream cryptographic processor which can efficiently and flexibly implement a variety of stream cipher algorithms.By analyzing the structure model,processing characteristics and storage characteristics of stream ciphers,a reconfigurable stream cryptographic processor with special instructions based on VLIW is presented,which has separate/cluster storage structure and is oriented to stream cipher operations.The proposed instruction structure can effectively support stream cipher processing with multiple data bit widths,parallelism among stream cipher processing with different data bit widths,and parallelism among branch control and stream cipher processing with high instruction level parallelism;the designed separate/clustered special bit registers and general register heaps,key register heaps can satisfy cryptographic requirements.So the proposed processor not only flexibly accomplishes the combination of multiple basic stream cipher operations to finish stream cipher algorithms.It has been implemented with 0.18μm CMOS technology,the test results show that the frequency can reach 200 MHz,and power consumption is 310 mw.Ten kinds of stream ciphers were realized in the processor.The key stream generation throughput of Grain-80,W7,MICKEY,ACHTERBAHN and Shrink algorithm is 100 Mbps,66.67 Mbps,66.67 Mbps,50 Mbps and 800 Mbps,respectively.The test result shows that the processor presented can achieve good tradeoff between high performance and flexibility of stream ciphers.展开更多
t In this paper an overall scheme of the task management system of ternary optical computer （TOC） is proposed, and the software architecture chart is given. The function and accomplishment of each module in the syst...t In this paper an overall scheme of the task management system of ternary optical computer （TOC） is proposed, and the software architecture chart is given. The function and accomplishment of each module in the system are described in general. In addition, according to the aforementioned scheme a prototype of TOC task management system is implemented, and the feasibility, rationality and completeness of the scheme are verified via running and testing the prototype.展开更多
An Efficient and flexible implementation of block ciphers is critical to achieve information security processing.Existing implementation methods such as GPP,FPGA and cryptographic application-specific ASIC provide the...An Efficient and flexible implementation of block ciphers is critical to achieve information security processing.Existing implementation methods such as GPP,FPGA and cryptographic application-specific ASIC provide the broad range of support.However,these methods could not achieve a good tradeoff between high-speed processing and flexibility.In this paper,we present a reconfigurable VLIW processor architecture targeted at block cipher processing,analyze basic operations and storage characteristics,and propose the multi-cluster register-file structure for block ciphers.As for the same operation element of block ciphers,we adopt reconfigurable technology for multiple cryptographic processing units and interconnection scheme.The proposed processor not only flexibly accomplishes the combination of multiple basic cryptographic operations,but also realizes dynamic configuration for cryptographic processing units.It has been implemented with0.18μm CMOS technology,the test results show that the frequency can reach 350 MHz.and power consumption is 420 mw.Ten kinds of block and hash ciphers were realized in the processor.The encryption throughput of AES,DES,IDEA,and SHA-1 algorithm is1554 Mbps,448Mbps,785 Mbps,and 424 Mbps respectively,the test result shows that our processor's encryption performance is significantly higher than other designs.展开更多
Objective:To review developments in sound processors over the past 30 years that have resulted in significant improvements in outcomes for Nucleus~ recipients.
A novel design of plate-type microchannel reactor has been developed for fuel cell-grade hydrogen production.Commercial Cu/Zn/Al2O3 was used as catalyst for the reforming reaction,and its effectiveness was evaluated o...A novel design of plate-type microchannel reactor has been developed for fuel cell-grade hydrogen production.Commercial Cu/Zn/Al2O3 was used as catalyst for the reforming reaction,and its effectiveness was evaluated on the mole fraction of products,methanol conversion,hydrogen yield and the amount of carbon monoxide under various operating conditions.Subsequently,0.5 wt% Ru/Al2O3 as methanation catalyst was prepared by impregnation method and coupled with MSR step to evaluate the capability of methanol processor for CO reduction.Based on the experimental results,the optimum conditions were obtained as feed flow rate of 5mL/h and temperature of 250℃,leading to a low CO selectivity and high H2 yield.The designed reformer with catalyst coated layer was compared with the conventional packed bed reformer at the same operating conditions.The constructed fuel processor had a good performance and excellent capability for on-board hydrogen production.展开更多
Fault tolerance in microprocessor systems has become a popular topic of architecture research. Much work has been done at different levels to accomplish reliability against soft errors, and some fault tolerance archit...Fault tolerance in microprocessor systems has become a popular topic of architecture research. Much work has been done at different levels to accomplish reliability against soft errors, and some fault tolerance architectures have been proposed. But little attention is paid to the thread level superscalar fault tolerance. This letter introduces microthread concept into superscalar processor fault tolerance domain, and puts forward a novel fault tolerance architecture, namely, MicroThread Based (MTB) coarse grained transient fault tolerance superscalar processor architecture, then discusses some detailed implementations.展开更多
A state equation for radical 4-degree-of-freedom active magnetic bearings isbuilt, and the approach on how to use linear quadratic method of optical control theory to design acentralized and decentralized parameters c...A state equation for radical 4-degree-of-freedom active magnetic bearings isbuilt, and the approach on how to use linear quadratic method of optical control theory to design acentralized and decentralized parameters control system is introduced, and also Matlab language isused to simulate and analyze. The simulation results have proved that the differences are smallbetween centralized parameters and decentralized parameters control system. The conclusions ofexperiments have shown that decentralized controllers designed from optimal state feedback theorymeet the requirements of active magnetic bearing system. The vibration amplitude of the rotor isabout 20 mu m when the speed of the rotor runs between 0 to 60 000 r/min. This method may be used inthe study and design of controllers of magnetic bearings.展开更多
Cloud computing has taken over the high-performance distributed computing area,and it currently provides on-demand services and resource polling over the web.As a result of constantly changing user service demand,the ...Cloud computing has taken over the high-performance distributed computing area,and it currently provides on-demand services and resource polling over the web.As a result of constantly changing user service demand,the task scheduling problem has emerged as a critical analytical topic in cloud computing.The primary goal of scheduling tasks is to distribute tasks to available processors to construct the shortest possible schedule without breaching precedence restrictions.Assignments and schedules of tasks substantially influence system operation in a heterogeneous multiprocessor system.The diverse processes inside the heuristic-based task scheduling method will result in varying makespan in the heterogeneous computing system.As a result,an intelligent scheduling algorithm should efficiently determine the priority of every subtask based on the resources necessary to lower the makespan.This research introduced a novel efficient scheduling task method in cloud computing systems based on the cooperation search algorithm to tackle an essential task and schedule a heterogeneous cloud computing problem.The basic idea of thismethod is to use the advantages of meta-heuristic algorithms to get the optimal solution.We assess our algorithm’s performance by running it through three scenarios with varying numbers of tasks.The findings demonstrate that the suggested technique beats existingmethods NewGenetic Algorithm(NGA),Genetic Algorithm(GA),Whale Optimization Algorithm(WOA),Gravitational Search Algorithm(GSA),and Hybrid Heuristic and Genetic(HHG)by 7.9%,2.1%,8.8%,7.7%,3.4%respectively according to makespan.展开更多
The concept and advantage of reconfigurable technology is introduced. A kind of processor architecture of re configurable macro processor (RMP) model based on FPGA array and DSP is put forward and has been implemented...The concept and advantage of reconfigurable technology is introduced. A kind of processor architecture of re configurable macro processor (RMP) model based on FPGA array and DSP is put forward and has been implemented. Two image algorithms are developed: template-based automatic target recognition and zone labeling. One is estimating for motion direction in the infrared image background, another is line picking-up algorithm based on image zone labeling and phase grouping technique. It is a kind of 'hardware' function that can be called by the DSP in high-level algorithm. It is also a kind of hardware algorithm of the DSP. The results of experiments show the reconfigurable computing technology based on RMP is an ideal accelerating means to deal with the high-speed image processing tasks. High real time performance is obtained in our two applications on RMP.展开更多
Slow speed of the Next-Generation sequencing data analysis, compared to the latest high throughput sequencers such as HiSeq X system, using the current industry standard genome analysis pipeline, has been the major fa...Slow speed of the Next-Generation sequencing data analysis, compared to the latest high throughput sequencers such as HiSeq X system, using the current industry standard genome analysis pipeline, has been the major factor of data backlog which limits the real-time use of genomic data for precision medicine. This study demonstrates the DRAGEN Bio-IT Processor as a potential candidate to remove the “Big Data Bottleneck”. DRAGENTM accomplished the variant calling, for ~40× coverage WGS data in as low as ~30 minutes using a single command, achieving the over 50-fold data analysis speed while maintaining the similar or better variant calling accuracy than the standard GATK Best Practices workflow. This systematic comparison provides the faster and efficient NGS data analysis alternative to NGS-based healthcare industries and research institutes to meet the requirement for precision medicine based healthcare.展开更多
This paper presents a design method of ByPassing Unit(BPU) in 32-bit Digital Signal Processor(DSP)-MD32. MD32 is realized in 0,18μm technology, 1.8V and 200 MHz working clock. It focuses on the Reduced Instruction Se...This paper presents a design method of ByPassing Unit(BPU) in 32-bit Digital Signal Processor(DSP)-MD32. MD32 is realized in 0,18μm technology, 1.8V and 200 MHz working clock. It focuses on the Reduced Instruction Set Computer(RISC) architecture and DSP computation capability thoroughly, extends DSP with various addressing modes in a customized DSP pipeline stage architecture. The paper also discusses the architecture and circuit design of bypassing logic to fit MD32 architecture. The parallel execution of BPU with instruction decode in architecture level is applied to reduce time delay. The optimization of circuit that serial select with priority is analyzed in detail, and the result shows that about half of time delay is reduced after this optimization. Examples show that BPU is useful for improving the DSP's performance.The forwarding logic in MD32 realizes 8 data channels feedback and meets the working clock limit.展开更多
文摘This paper presents a smart compensation system based on MCA7707 (a kind of signal processor). The li near errors and high order errors of a sensor (especially piezoresistive sensor) can be corrected by using this system. It can optimize the process of piezoresi stive sensor calibration and compensation, then, a total error factor within 0.2 % of the sensor′s repeatability errors is obtained. Data are recorded and coeff icients are determined automatically by this system, thus, the sensor compensati on is simplified greatly. For operating easily, a wizard compensation program is designed to correct every error and to get the optimum compensation.
基金Supported by the Guangzhou Key Technology R&D Program (No. 2007Z2-D0011)
文摘Java technology is spreading rapidly all over the world in recent years. It is a popular application development language for its well-encapsulation, platform-independent and high security. There are great amounts of Java games and other gadgets on mobile platforms, as well as on set-up-box systems. As Java applications become more sophisticated, the Java Virtual Machine (JVM) mid-dle-wares in embedded systems are not satisfying, Java-specific chips extend in the market. All existing Java-based system software or Operating System (OS) are used on JVM, they cannot be used on Java processors. It is important to develop a pure Java system software or OS so that embedded systems using Java processors will have great performance in Java applications. This paper presents a set of system software designed for a Java-specified processor VP6K, which is also a System-on-Chip (SoC). This system software includes real-time multitask dispatching, file management, device management, hardware drivers, and infrastructural Application Programming Interface (APIs). According to ex-perimental results, the system software provides interfaces for Java programs to fully handle CPU resource, so that all applications can be executed properly and efficiently. VP6K embedded platform shows its good performance for Java applications when the system software is implemented.
基金supported by National Natural Science Foundation of China(No.50375054)China Postdoctoral Science Foundation(No.20060400745).
文摘A fuzzy logic intelligent control system of pulsed MAG welding inverter based on digital signal processor(DSP)is proposed to obtain the consistency of arc length in pulsed MAG welding.The proposed control system combines the merits of intelligent control with DSP digital control.The fuzzy logic intelligent control system designed is a typical two-input-single-output structure,and regards the error and the change in error of peak arc voltage as two inputs and the background time as single output.The fuzzy logic intelligent control system is realized in a look-up table(LUT)method by using MATLAB based fuzzy logic toolbox,and the implement of LUT method based on DSP is also discussed.The pulsed MAG welding experimental results demonstrate that the developed fuzzy logic intelligent control system based on DSP has strong arc length controlling ability to accomplish the stable pulsed MAG welding process and controls pulsed MAG welding inverter digitally and intelligently.
文摘A team of researchers from the University of Science and Technology of China(USTC)of the Chinese Academy of Sciences(CAS)and its partners have made significant advancements in random quantum circuit sampling with Zuchongzhi-3,a superconducting quantum computing prototype featuring 105 qubits and 182 couplers.
文摘目前,多核实时系统中同步任务的节能调度研究主要针对的是同构多核处理器平台,而异构多核处理器架构能够更有效地发挥系统性能。将现有的研究直接应用于异构多核系统,在保证可调度性的情况下会导致能耗变高。对此,通过使用动态电压与频率调节(Dynamic Voltage Frequency Scaling,DVFS)技术,研究异构多核实时系统中基于任务同步的节能调度问题,提出同步感知的最大能耗节省优先算法(Synchronization Aware-Largest Energy Saved First,SA-LESF)。该算法针对所有任务的速度配置进行迭代优化,直至所有任务均达到其最大限度节能的速度配置。此外,进一步提出基于动态松弛时间回收的同步感知最大能耗节省优先算法(Synchronization Aware-Largest Energy Saved First with Dynamic Reclamation,SA-LESF-DR)。该算法在保证实时任务可调度的同时,实施相应的回收策略,进一步降低系统能耗。实验结果表明,SA-LESF与SA-LESF-DR算法在能耗表现上具有优势,在相同任务集下,相比其他算法可节省高达30%的能耗。
基金the National Natural Science Foundation of China(No.60475018)~~
文摘This paper proposes a cochlear prosthetic system with an implanted digital signal processor （DSP）. This system transmits voice-band signals with a low data rate through the wireless link, free of the data-rate limitation and suitable for future development. By optimizing the speech processing algorithm and the DSP hardware design, the implanted DSP manages to execute the continuous interleaved sampling （CIS） algorithm at a clock frequency of 3MHz and a power consumption of only 1.91mW. With an analytic power-transmission efficiency of the wireless inductive link （40%）, the power overhead caused by the implanted DSP is derived as 2.87roW,which is trivial when compared with the power consumption of existing cochlear prosthetic systems （tens of milliwatts）. With the DSP implanted,this new system can.be easily developed into a fully implanted cochlear prosthesis.
基金supported by the National "863" Project of China (Nos. 2007AA06Z112,2007AA03Z446 and 2009AA03Z442)the National Natural Science Foundation of China (No.61077074)the Science and Technology Department of Jilin Province of China (Nos. 20070709 and 20090422)
文摘Considering that the noises resulting from low modulation frequency are serious and cannot be totally eliminated by the classic filters,a novel infrared(IR) gas concentration detection system based on the least square fast transverse filtering(LS-FTF) self-adaptive modern filter structure is proposed.The principle,procedure and simulation on the LS-FTF algorithm are described.The system schematic diagram and key techniques are discussed.The procedures for the ARM7 processor,including LS-FTF and main program,are demonstrated.Comparisons between the experimental results of the detection system using the LS-FTF algorithm and those of the system without using this algorithm are performed.By using the LS-FTF algorithm,the maximum detection error is decreased from 14.3 to 5.4,and also the detection stability increases as the variation range of the relative error becomes much smaller.The proposed LS-FTF self-adaptive denoising method can be of practical value for mid-IR gas detection,especially for weak signal detection.
基金supported by National Natural Science Foundation of China with granted No.61404175
文摘As an important branch of information security algorithms,the efficient and flexible implementation of stream ciphers is vital.Existing implementation methods,such as FPGA,GPP and ASIC,provide a good support,but they could not achieve a better tradeoff between high speed processing and high flexibility.ASIC has fast processing speed,but its flexibility is poor,GPP has high flexibility,but the processing speed is slow,FPGA has high flexibility and processing speed,but the resource utilization is very low.This paper studies a stream cryptographic processor which can efficiently and flexibly implement a variety of stream cipher algorithms.By analyzing the structure model,processing characteristics and storage characteristics of stream ciphers,a reconfigurable stream cryptographic processor with special instructions based on VLIW is presented,which has separate/cluster storage structure and is oriented to stream cipher operations.The proposed instruction structure can effectively support stream cipher processing with multiple data bit widths,parallelism among stream cipher processing with different data bit widths,and parallelism among branch control and stream cipher processing with high instruction level parallelism;the designed separate/clustered special bit registers and general register heaps,key register heaps can satisfy cryptographic requirements.So the proposed processor not only flexibly accomplishes the combination of multiple basic stream cipher operations to finish stream cipher algorithms.It has been implemented with 0.18μm CMOS technology,the test results show that the frequency can reach 200 MHz,and power consumption is 310 mw.Ten kinds of stream ciphers were realized in the processor.The key stream generation throughput of Grain-80,W7,MICKEY,ACHTERBAHN and Shrink algorithm is 100 Mbps,66.67 Mbps,66.67 Mbps,50 Mbps and 800 Mbps,respectively.The test result shows that the processor presented can achieve good tradeoff between high performance and flexibility of stream ciphers.
基金Project supported by the National Natural Science Foundation of China(Grant No.61073049)the Ph D Programs Foundation of the Ministry of Education of China(Grant No.20093108110016)the Shanghai Leading Academic Discipline Project(Grant No.J50103)
文摘t In this paper an overall scheme of the task management system of ternary optical computer （TOC） is proposed, and the software architecture chart is given. The function and accomplishment of each module in the system are described in general. In addition, according to the aforementioned scheme a prototype of TOC task management system is implemented, and the feasibility, rationality and completeness of the scheme are verified via running and testing the prototype.
基金supported by National Natural Science Foundation of China with granted No.61404175
文摘An Efficient and flexible implementation of block ciphers is critical to achieve information security processing.Existing implementation methods such as GPP,FPGA and cryptographic application-specific ASIC provide the broad range of support.However,these methods could not achieve a good tradeoff between high-speed processing and flexibility.In this paper,we present a reconfigurable VLIW processor architecture targeted at block cipher processing,analyze basic operations and storage characteristics,and propose the multi-cluster register-file structure for block ciphers.As for the same operation element of block ciphers,we adopt reconfigurable technology for multiple cryptographic processing units and interconnection scheme.The proposed processor not only flexibly accomplishes the combination of multiple basic cryptographic operations,but also realizes dynamic configuration for cryptographic processing units.It has been implemented with0.18μm CMOS technology,the test results show that the frequency can reach 350 MHz.and power consumption is 420 mw.Ten kinds of block and hash ciphers were realized in the processor.The encryption throughput of AES,DES,IDEA,and SHA-1 algorithm is1554 Mbps,448Mbps,785 Mbps,and 424 Mbps respectively,the test result shows that our processor's encryption performance is significantly higher than other designs.
基金funded by Cochlear Limited,the manufacturer of Nucleus implant systems
文摘Objective:To review developments in sound processors over the past 30 years that have resulted in significant improvements in outcomes for Nucleus~ recipients.
基金supported by the Iran National Science Foundation (INSF)
文摘A novel design of plate-type microchannel reactor has been developed for fuel cell-grade hydrogen production.Commercial Cu/Zn/Al2O3 was used as catalyst for the reforming reaction,and its effectiveness was evaluated on the mole fraction of products,methanol conversion,hydrogen yield and the amount of carbon monoxide under various operating conditions.Subsequently,0.5 wt% Ru/Al2O3 as methanation catalyst was prepared by impregnation method and coupled with MSR step to evaluate the capability of methanol processor for CO reduction.Based on the experimental results,the optimum conditions were obtained as feed flow rate of 5mL/h and temperature of 250℃,leading to a low CO selectivity and high H2 yield.The designed reformer with catalyst coated layer was compared with the conventional packed bed reformer at the same operating conditions.The constructed fuel processor had a good performance and excellent capability for on-board hydrogen production.
文摘Fault tolerance in microprocessor systems has become a popular topic of architecture research. Much work has been done at different levels to accomplish reliability against soft errors, and some fault tolerance architectures have been proposed. But little attention is paid to the thread level superscalar fault tolerance. This letter introduces microthread concept into superscalar processor fault tolerance domain, and puts forward a novel fault tolerance architecture, namely, MicroThread Based (MTB) coarse grained transient fault tolerance superscalar processor architecture, then discusses some detailed implementations.
基金This project is supported by Aeronautic Science Foundation (No.98C52052) National Natural Science Foundation of China (No.50275067, No.60174052).
文摘A state equation for radical 4-degree-of-freedom active magnetic bearings isbuilt, and the approach on how to use linear quadratic method of optical control theory to design acentralized and decentralized parameters control system is introduced, and also Matlab language isused to simulate and analyze. The simulation results have proved that the differences are smallbetween centralized parameters and decentralized parameters control system. The conclusions ofexperiments have shown that decentralized controllers designed from optimal state feedback theorymeet the requirements of active magnetic bearing system. The vibration amplitude of the rotor isabout 20 mu m when the speed of the rotor runs between 0 to 60 000 r/min. This method may be used inthe study and design of controllers of magnetic bearings.
文摘Cloud computing has taken over the high-performance distributed computing area,and it currently provides on-demand services and resource polling over the web.As a result of constantly changing user service demand,the task scheduling problem has emerged as a critical analytical topic in cloud computing.The primary goal of scheduling tasks is to distribute tasks to available processors to construct the shortest possible schedule without breaching precedence restrictions.Assignments and schedules of tasks substantially influence system operation in a heterogeneous multiprocessor system.The diverse processes inside the heuristic-based task scheduling method will result in varying makespan in the heterogeneous computing system.As a result,an intelligent scheduling algorithm should efficiently determine the priority of every subtask based on the resources necessary to lower the makespan.This research introduced a novel efficient scheduling task method in cloud computing systems based on the cooperation search algorithm to tackle an essential task and schedule a heterogeneous cloud computing problem.The basic idea of thismethod is to use the advantages of meta-heuristic algorithms to get the optimal solution.We assess our algorithm’s performance by running it through three scenarios with varying numbers of tasks.The findings demonstrate that the suggested technique beats existingmethods NewGenetic Algorithm(NGA),Genetic Algorithm(GA),Whale Optimization Algorithm(WOA),Gravitational Search Algorithm(GSA),and Hybrid Heuristic and Genetic(HHG)by 7.9%,2.1%,8.8%,7.7%,3.4%respectively according to makespan.
文摘The concept and advantage of reconfigurable technology is introduced. A kind of processor architecture of re configurable macro processor (RMP) model based on FPGA array and DSP is put forward and has been implemented. Two image algorithms are developed: template-based automatic target recognition and zone labeling. One is estimating for motion direction in the infrared image background, another is line picking-up algorithm based on image zone labeling and phase grouping technique. It is a kind of 'hardware' function that can be called by the DSP in high-level algorithm. It is also a kind of hardware algorithm of the DSP. The results of experiments show the reconfigurable computing technology based on RMP is an ideal accelerating means to deal with the high-speed image processing tasks. High real time performance is obtained in our two applications on RMP.
文摘Slow speed of the Next-Generation sequencing data analysis, compared to the latest high throughput sequencers such as HiSeq X system, using the current industry standard genome analysis pipeline, has been the major factor of data backlog which limits the real-time use of genomic data for precision medicine. This study demonstrates the DRAGEN Bio-IT Processor as a potential candidate to remove the “Big Data Bottleneck”. DRAGENTM accomplished the variant calling, for ~40× coverage WGS data in as low as ~30 minutes using a single command, achieving the over 50-fold data analysis speed while maintaining the similar or better variant calling accuracy than the standard GATK Best Practices workflow. This systematic comparison provides the faster and efficient NGS data analysis alternative to NGS-based healthcare industries and research institutes to meet the requirement for precision medicine based healthcare.
基金Supported by the National High Technology Research & Development Program of China (863 Program) (2002AA1Z1140).
文摘This paper presents a design method of ByPassing Unit(BPU) in 32-bit Digital Signal Processor(DSP)-MD32. MD32 is realized in 0,18μm technology, 1.8V and 200 MHz working clock. It focuses on the Reduced Instruction Set Computer(RISC) architecture and DSP computation capability thoroughly, extends DSP with various addressing modes in a customized DSP pipeline stage architecture. The paper also discusses the architecture and circuit design of bypassing logic to fit MD32 architecture. The parallel execution of BPU with instruction decode in architecture level is applied to reduce time delay. The optimization of circuit that serial select with priority is analyzed in detail, and the result shows that about half of time delay is reduced after this optimization. Examples show that BPU is useful for improving the DSP's performance.The forwarding logic in MD32 realizes 8 data channels feedback and meets the working clock limit.
