Vector architectures are widely employed in modern processors due to their high performance and energy efficiency in exploiting data-level parallelism through single instruction multiple data(SIMD)paradigms.The built-...Vector architectures are widely employed in modern processors due to their high performance and energy efficiency in exploiting data-level parallelism through single instruction multiple data(SIMD)paradigms.The built-in scalar cores and the vector processing units(VPUs)can be organized as integrated or decoupled.The decoupled vector architecture primarily offers the advantage of independent operation,allowing the VPU and the scalar core to execute concurrently at different frequencies,enhancing overall throughput and performance.This enables specialized VPU optimization for long vectors,complex vector operations,and separate power management,which excels in computation-intensive applications.This paper comprehensively reviews processors with decoupled VPUs,discussing their advantages and various implementations.Design challenges and corresponding potential solutions are also be included.展开更多
Resistive Random Access Memory(ReRAM)-based neural network accelerators have potential to surpass their digital counterparts in computational efficiency and performance.However,design of these accelerators faces a num...Resistive Random Access Memory(ReRAM)-based neural network accelerators have potential to surpass their digital counterparts in computational efficiency and performance.However,design of these accelerators faces a number of challenges including imperfections of the Re RAM device and a large amount of calculations required to accurately simulate the former.We present XB-SIM,a simulation framework for Re RAM-crossbar-based Convolutional Neural Network(CNN)accelerators.XB-SIM can be flexibly configured to simulate the accelerator’s structure and clock-driven behaviors at the architecture level.This framework also includes an Re RAM-aware Neural Network(NN)training algorithm and a CNN-oriented mapper to train an NN and map it onto the simulated design efficiently.Behavior of the simulator has been verified by the corresponding circuit simulation of a real chip.Furthermore,a batch processing mode of the massive calculations that are required to mimic the behavior of Re RAM-crossbar circuits is proposed to fully apply the computational concurrency of the mapping strategy.On CPU/GPGPU,this batch processing mode can improve the simulation speed by up to 5.02 or 34.29.Within this framework,comprehensive architectural exploration and end-to-end evaluation have been achieved,which provide some insights for systemic optimization.展开更多
基金supported by the National Natural Science Foundation of China under Grant Nos.62032001 and 62472436.
文摘Vector architectures are widely employed in modern processors due to their high performance and energy efficiency in exploiting data-level parallelism through single instruction multiple data(SIMD)paradigms.The built-in scalar cores and the vector processing units(VPUs)can be organized as integrated or decoupled.The decoupled vector architecture primarily offers the advantage of independent operation,allowing the VPU and the scalar core to execute concurrently at different frequencies,enhancing overall throughput and performance.This enables specialized VPU optimization for long vectors,complex vector operations,and separate power management,which excels in computation-intensive applications.This paper comprehensively reviews processors with decoupled VPUs,discussing their advantages and various implementations.Design challenges and corresponding potential solutions are also be included.
基金supported in part by Beijing Academy of Artificial Intelligence(BAAI)(No.BAAI2019ZD0403)Beijing Innovation Center for Future Chip,Tsinghua Universitythe Science and Technology Innovation Special Zone Project,China。
文摘Resistive Random Access Memory(ReRAM)-based neural network accelerators have potential to surpass their digital counterparts in computational efficiency and performance.However,design of these accelerators faces a number of challenges including imperfections of the Re RAM device and a large amount of calculations required to accurately simulate the former.We present XB-SIM,a simulation framework for Re RAM-crossbar-based Convolutional Neural Network(CNN)accelerators.XB-SIM can be flexibly configured to simulate the accelerator’s structure and clock-driven behaviors at the architecture level.This framework also includes an Re RAM-aware Neural Network(NN)training algorithm and a CNN-oriented mapper to train an NN and map it onto the simulated design efficiently.Behavior of the simulator has been verified by the corresponding circuit simulation of a real chip.Furthermore,a batch processing mode of the massive calculations that are required to mimic the behavior of Re RAM-crossbar circuits is proposed to fully apply the computational concurrency of the mapping strategy.On CPU/GPGPU,this batch processing mode can improve the simulation speed by up to 5.02 or 34.29.Within this framework,comprehensive architectural exploration and end-to-end evaluation have been achieved,which provide some insights for systemic optimization.
