Three-dimensional(3D)single molecule localization microscopy(SMLM)plays an important role in biomedical applications,but its data processing is very complicated.Deep learning is a potential tool to solve this problem....Three-dimensional(3D)single molecule localization microscopy(SMLM)plays an important role in biomedical applications,but its data processing is very complicated.Deep learning is a potential tool to solve this problem.As the state of art 3D super-resolution localization algorithm based on deep learning,FD-DeepLoc algorithm reported recently still has a gap with the expected goal of online image processing,even though it has greatly improved the data processing throughput.In this paper,a new algorithm Lite-FD-DeepLoc is developed on the basis of FD-DeepLoc algorithm to meet the online image processing requirements of 3D SMLM.This new algorithm uses the feature compression method to reduce the parameters of the model,and combines it with pipeline programming to accelerate the inference process of the deep learning model.The simulated data processing results show that the image processing speed of Lite-FD-DeepLoc is about twice as fast as that of FD-DeepLoc with a slight decrease in localization accuracy,which can realize real-time processing of 256×256 pixels size images.The results of biological experimental data processing imply that Lite-FD-DeepLoc can successfully analyze the data based on astigmatism and saddle point engineering,and the global resolution of the reconstructed image is equivalent to or even better than FD-DeepLoc algorithm.展开更多
The packet classification is a fundamental process in provisioning security and quality of service for many intelligent network-embedded systems running in the Internet of Things(IoT).In recent years,researchers have ...The packet classification is a fundamental process in provisioning security and quality of service for many intelligent network-embedded systems running in the Internet of Things(IoT).In recent years,researchers have tried to develop hardware-based solutions for the classification of Internet packets.Due to higher throughput and shorter delays,these solutions are considered as a major key to improving the quality of services.Most of these efforts have attempted to implement a software algorithm on the FPGA to reduce the processing time and enhance the throughput.The proposed architectures,however,cannot reach a compromise among power consumption,memory usage,and throughput rate.In view of this,the architecture proposed in this paper contains a pipelinebased micro-core that is used in network processors to classify packets.To this end,three architectures have been implemented using the proposed micro-core.The first architecture performs parallel classification based on header fields.The second one classifies packets in a serial manner.The last architecture is the pipeline-based classifier,which can increase performance by nine times.The proposed architectures have been implemented on an FPGA chip.The results are indicative of a reduction in memory usage as well as an increase in speedup and throughput.The architecture has a power consumption of is 1.294w,and its throughput with a frequency of 233 MHz exceeds 147 Gbps.展开更多
Hilly terrain pipeline is a common form of pipeline in oil and gas storage and transportation industry.Due to the hilly terrain influence, the liquid at the elbow of the gathering pipeline is easy to flow back and acc...Hilly terrain pipeline is a common form of pipeline in oil and gas storage and transportation industry.Due to the hilly terrain influence, the liquid at the elbow of the gathering pipeline is easy to flow back and accumulate to form slug flow, so it is necessary to remove the accumulated liquid by gas purging. In this paper, experiment is carried out in hilly terrain pipelines. Three flow patterns of stratified flow, slug flow and stratified entrained flow are observed. The process of gas purging accumulated liquid is divided into four stages, namely liquid accumulation, liquid rising, continuous outflow and tail outflow. At the same time, the flow pattern maps of each stage are drawn. The pressure drop signal is analyzed in time domain and frequency domain, and the contour map of pressure drop distribution is drawn. It is found that the ratio of range to average value can well distinguish the occurrence range of each flow pattern.Based on visualization, the transition process of slug flow to stratified flow and stratified entrained flow is studied, and the transition boundary prediction model is established. An image processing method is proposed to convert the image signal into a similarity curve, and PSD analysis is performed to calculate the slug frequency. The normal distribution is used to fit the slug frequency, and the predicted correlation is in good agreement with the experimental data.展开更多
A low-power-consumption 9bit 10MS/s pipeline ADC,used in a CMOS image sensor,is proposed. In the design, the decrease of power consumption is achieved by applying low-power-consumption and large-output-swing amplifier...A low-power-consumption 9bit 10MS/s pipeline ADC,used in a CMOS image sensor,is proposed. In the design, the decrease of power consumption is achieved by applying low-power-consumption and large-output-swing amplifiers with gain boost structure, and biasing all the cells with the same voltage bias source, which requires careful layout design and large capacitors. In addition,capacitor array DAC is also applied to reduce power consumption,and low threshold voltage MOS transistors are used to achieve a large signal processing range. The ADC was implemented in a 0.18μm 4M-1 P CMOS process,and the experimental results indicate that it consumes only 7mW, which is much less than general pipeline ADCs. The ADC was used in a 300000 pixels CMOS image sensor.展开更多
基金supported by the Start-up Fund from Hainan University(No.KYQD(ZR)-20077)。
文摘Three-dimensional(3D)single molecule localization microscopy(SMLM)plays an important role in biomedical applications,but its data processing is very complicated.Deep learning is a potential tool to solve this problem.As the state of art 3D super-resolution localization algorithm based on deep learning,FD-DeepLoc algorithm reported recently still has a gap with the expected goal of online image processing,even though it has greatly improved the data processing throughput.In this paper,a new algorithm Lite-FD-DeepLoc is developed on the basis of FD-DeepLoc algorithm to meet the online image processing requirements of 3D SMLM.This new algorithm uses the feature compression method to reduce the parameters of the model,and combines it with pipeline programming to accelerate the inference process of the deep learning model.The simulated data processing results show that the image processing speed of Lite-FD-DeepLoc is about twice as fast as that of FD-DeepLoc with a slight decrease in localization accuracy,which can realize real-time processing of 256×256 pixels size images.The results of biological experimental data processing imply that Lite-FD-DeepLoc can successfully analyze the data based on astigmatism and saddle point engineering,and the global resolution of the reconstructed image is equivalent to or even better than FD-DeepLoc algorithm.
文摘The packet classification is a fundamental process in provisioning security and quality of service for many intelligent network-embedded systems running in the Internet of Things(IoT).In recent years,researchers have tried to develop hardware-based solutions for the classification of Internet packets.Due to higher throughput and shorter delays,these solutions are considered as a major key to improving the quality of services.Most of these efforts have attempted to implement a software algorithm on the FPGA to reduce the processing time and enhance the throughput.The proposed architectures,however,cannot reach a compromise among power consumption,memory usage,and throughput rate.In view of this,the architecture proposed in this paper contains a pipelinebased micro-core that is used in network processors to classify packets.To this end,three architectures have been implemented using the proposed micro-core.The first architecture performs parallel classification based on header fields.The second one classifies packets in a serial manner.The last architecture is the pipeline-based classifier,which can increase performance by nine times.The proposed architectures have been implemented on an FPGA chip.The results are indicative of a reduction in memory usage as well as an increase in speedup and throughput.The architecture has a power consumption of is 1.294w,and its throughput with a frequency of 233 MHz exceeds 147 Gbps.
基金supported by the Basic Science Center Program for Ordered Energy Conversion of the National Natural Science Foundation of China(No.52488201)the National Natural Science Foundation of China(No.52422606).
文摘Hilly terrain pipeline is a common form of pipeline in oil and gas storage and transportation industry.Due to the hilly terrain influence, the liquid at the elbow of the gathering pipeline is easy to flow back and accumulate to form slug flow, so it is necessary to remove the accumulated liquid by gas purging. In this paper, experiment is carried out in hilly terrain pipelines. Three flow patterns of stratified flow, slug flow and stratified entrained flow are observed. The process of gas purging accumulated liquid is divided into four stages, namely liquid accumulation, liquid rising, continuous outflow and tail outflow. At the same time, the flow pattern maps of each stage are drawn. The pressure drop signal is analyzed in time domain and frequency domain, and the contour map of pressure drop distribution is drawn. It is found that the ratio of range to average value can well distinguish the occurrence range of each flow pattern.Based on visualization, the transition process of slug flow to stratified flow and stratified entrained flow is studied, and the transition boundary prediction model is established. An image processing method is proposed to convert the image signal into a similarity curve, and PSD analysis is performed to calculate the slug frequency. The normal distribution is used to fit the slug frequency, and the predicted correlation is in good agreement with the experimental data.
文摘A low-power-consumption 9bit 10MS/s pipeline ADC,used in a CMOS image sensor,is proposed. In the design, the decrease of power consumption is achieved by applying low-power-consumption and large-output-swing amplifiers with gain boost structure, and biasing all the cells with the same voltage bias source, which requires careful layout design and large capacitors. In addition,capacitor array DAC is also applied to reduce power consumption,and low threshold voltage MOS transistors are used to achieve a large signal processing range. The ADC was implemented in a 0.18μm 4M-1 P CMOS process,and the experimental results indicate that it consumes only 7mW, which is much less than general pipeline ADCs. The ADC was used in a 300000 pixels CMOS image sensor.
