In Present scenario battery-powered hand-held multimedia systems become popular. The power consumption in these devices is a major concern these days for its long operational life. Although various techniques to reduc...In Present scenario battery-powered hand-held multimedia systems become popular. The power consumption in these devices is a major concern these days for its long operational life. Although various techniques to reduce the power dissipation has been developed. The most adopted method is to lower the supply voltage. But lowering the Vdd reduces the gate current much more rapidly than the sub-threshold current and degrades the SNM. This degraded SNM further limits the voltage scaling. To improve the stability of the SRAM cell topology of the conventional 6T Static Random Access Memory (SRAM) cell has been changed and revised to 8T and 10T cell, the topologies. This work has analyzed the SRAM’s Static Noise Margin (SNM) at 8T for various process corners at 65nm technology. It evaluates the SNM along with the write margins of the cell along with the cell size of 8T SRAM bit-cell operating in sub-threshold voltage at various process corners. It is observed that an 8T cell has 13 % better write margin than conventional 6T SRAM cell. This paper analyses the dependence of SNM of SRAM memory cell on supply voltage, temperature, transistor sizing in 65nm technology at various process corners (TT, SS, FF, FS, and SF).展开更多
Due to the continuous rising demand of handheld devices like iPods, mobile, tablets;specific applications like biomedical applications like pacemakers, hearing aid machines and space applications which require stable ...Due to the continuous rising demand of handheld devices like iPods, mobile, tablets;specific applications like biomedical applications like pacemakers, hearing aid machines and space applications which require stable digital systems with low power consumptions are required. As a main part in digital system the SRAM (Static Random Access Memory) should have low power consumption and stability. As we are continuously moving towards scaling for the last two decades the effect of this is process variations which have severe effect on stability, performance. Reducing the supply voltage to sub-threshold region, which helps in reducing the power consumption to an extent but side by side it raises the issue of the stability of the memory. Static Noise Margin of SRAM cell enforces great challenges to the sub threshold SRAM design. In this paper we have analyzed the cell stability of 9T SRAM Cell at various processes. The cell stability is checked at deep submicron (DSM) technology. In this paper we have analyzed the effect of temperature and supply voltage (Vdd) on the stability parameters of SRAM which is Static Noise Margin (SNM), Write Margin (WM) and Read Current. The effect has been observed at various process corners at 45 nm technology. The temperature has a significant effect on stability along with the Vdd. The Cell has been working efficiently at all process corners and has 50% more SNM from conventional 6T SRAM and 30% more WM from conventional 6T SRAM cell.展开更多
In this study we performed a classical spectrum analysis of seismic waveforms recorded at far field stations of the great MW7.9 Wenchuan earthquake to observe the shifts of the corner frequency with azimuth due to the...In this study we performed a classical spectrum analysis of seismic waveforms recorded at far field stations of the great MW7.9 Wenchuan earthquake to observe the shifts of the corner frequency with azimuth due to the Doppler effect.Our results show that this damaging great earthquake had a dominating rupture propagation direction of 64.0°.The equivalent radius of the fault rupture surface was estimated to be 33 km,yielding the rupture area of about 3 500 km2.Thus the length of the rupture fault surface is about 230 km if the depth（or width） extent is 15 km.The computer program developed in this study can quickly provide the information about the source of a future large（damaging） earthquake,which could be very useful for predicting aftershocks and planning the rescue operations.展开更多
The precise compact modeling of magnetic devices is pivotal for the integrated design of spin-transfer torque magnetic tunnel junction(STT-MTJ)in conjunction with CMOS circuitry.This work presents a macro model for an...The precise compact modeling of magnetic devices is pivotal for the integrated design of spin-transfer torque magnetic tunnel junction(STT-MTJ)in conjunction with CMOS circuitry.This work presents a macro model for an STT-MTJ which is compatible with SPICE simulation platforms.The model accurately replicates the electrical performance of the MTJ,encompassing the resistance-voltage characteristics and the pulse-width-dependent state switching behavior,and is validated with various experimental data.Additionally,the impact of process variations,particularly those affecting the MTJ diameter and barrier thickness is investigated and summarized in a corner model.Monte Carlo simulations demonstrate that our adaptable and streamlined model can be efficiently incorporated into the design of integrated circuits.展开更多
文摘In Present scenario battery-powered hand-held multimedia systems become popular. The power consumption in these devices is a major concern these days for its long operational life. Although various techniques to reduce the power dissipation has been developed. The most adopted method is to lower the supply voltage. But lowering the Vdd reduces the gate current much more rapidly than the sub-threshold current and degrades the SNM. This degraded SNM further limits the voltage scaling. To improve the stability of the SRAM cell topology of the conventional 6T Static Random Access Memory (SRAM) cell has been changed and revised to 8T and 10T cell, the topologies. This work has analyzed the SRAM’s Static Noise Margin (SNM) at 8T for various process corners at 65nm technology. It evaluates the SNM along with the write margins of the cell along with the cell size of 8T SRAM bit-cell operating in sub-threshold voltage at various process corners. It is observed that an 8T cell has 13 % better write margin than conventional 6T SRAM cell. This paper analyses the dependence of SNM of SRAM memory cell on supply voltage, temperature, transistor sizing in 65nm technology at various process corners (TT, SS, FF, FS, and SF).
文摘Due to the continuous rising demand of handheld devices like iPods, mobile, tablets;specific applications like biomedical applications like pacemakers, hearing aid machines and space applications which require stable digital systems with low power consumptions are required. As a main part in digital system the SRAM (Static Random Access Memory) should have low power consumption and stability. As we are continuously moving towards scaling for the last two decades the effect of this is process variations which have severe effect on stability, performance. Reducing the supply voltage to sub-threshold region, which helps in reducing the power consumption to an extent but side by side it raises the issue of the stability of the memory. Static Noise Margin of SRAM cell enforces great challenges to the sub threshold SRAM design. In this paper we have analyzed the cell stability of 9T SRAM Cell at various processes. The cell stability is checked at deep submicron (DSM) technology. In this paper we have analyzed the effect of temperature and supply voltage (Vdd) on the stability parameters of SRAM which is Static Noise Margin (SNM), Write Margin (WM) and Read Current. The effect has been observed at various process corners at 45 nm technology. The temperature has a significant effect on stability along with the Vdd. The Cell has been working efficiently at all process corners and has 50% more SNM from conventional 6T SRAM and 30% more WM from conventional 6T SRAM cell.
文摘In this study we performed a classical spectrum analysis of seismic waveforms recorded at far field stations of the great MW7.9 Wenchuan earthquake to observe the shifts of the corner frequency with azimuth due to the Doppler effect.Our results show that this damaging great earthquake had a dominating rupture propagation direction of 64.0°.The equivalent radius of the fault rupture surface was estimated to be 33 km,yielding the rupture area of about 3 500 km2.Thus the length of the rupture fault surface is about 230 km if the depth（or width） extent is 15 km.The computer program developed in this study can quickly provide the information about the source of a future large（damaging） earthquake,which could be very useful for predicting aftershocks and planning the rescue operations.
基金Project supported by the National Science and Technology Major Project of China(Grant No.2020AAA0109003)。
文摘The precise compact modeling of magnetic devices is pivotal for the integrated design of spin-transfer torque magnetic tunnel junction(STT-MTJ)in conjunction with CMOS circuitry.This work presents a macro model for an STT-MTJ which is compatible with SPICE simulation platforms.The model accurately replicates the electrical performance of the MTJ,encompassing the resistance-voltage characteristics and the pulse-width-dependent state switching behavior,and is validated with various experimental data.Additionally,the impact of process variations,particularly those affecting the MTJ diameter and barrier thickness is investigated and summarized in a corner model.Monte Carlo simulations demonstrate that our adaptable and streamlined model can be efficiently incorporated into the design of integrated circuits.
