This paper presents the power hardware in the loop(PHIL)validation of a feed forward DC voltage control scheme for the fault ride through(FRT)of voltage source converter(VSC)high voltage DC(HVDC)connected offshore win...This paper presents the power hardware in the loop(PHIL)validation of a feed forward DC voltage control scheme for the fault ride through(FRT)of voltage source converter(VSC)high voltage DC(HVDC)connected offshore wind power plants(WPPs).In the proposed FRT scheme,the WPP collector network AC voltage is actively controlled by considering both the DC voltage error and the AC current from the WPP AC collector system which ensures fast and robust FRT of the VSC HVDC connected offshore WPPs.The PHIL tests were carried out in order to verify the efficacy of the proposed feed forward DC voltage control scheme for enhancing the FRT capability of the VSC HVDC connected WPPs.The PHIL test results have demonstrated the proper control coordination between the offshore WPP and the WPP side VSC and the efficient FRT of the VSC HVDC connected WPPs.展开更多
There is increasing interest in the evaluation of wind turbine control capabilities for providing grid support.Power hardware in the loop(PHIL)simulation is an advanced method that can be used for studying the interac...There is increasing interest in the evaluation of wind turbine control capabilities for providing grid support.Power hardware in the loop(PHIL)simulation is an advanced method that can be used for studying the interaction of hardware with the power network,as the scaled-down actual wind turbine is connected with a simulated system through an amplifier.Special consideration must be made in the design of the PHIL platform to ensure that the system is stable and yields accurate results.This paper presents a method for stabilizing the PHIL interface and improving the accuracy of PHIL simulation in a real-time application.The method factors in both the power and voltage scaling level,and a phase compensation scheme.It uses the reactive power control capability of the wind turbine inverter to eliminate the phase shift imposed by the feedback current filter.This is accomplished with no negative impact on the dynamic behavior of the wind turbine.The PHIL simulation results demonstrate the effectiveness of the proposed stability analysis method and phase compensation scheme.The strength of the platform is demonstrated by extending the simulation method to wind turbine control validation.展开更多
In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time embedded system working in the low workload situation, the energy efficiency of the hardware m...In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time embedded system working in the low workload situation, the energy efficiency of the hardware multithread is discussed and a novel dynamic multithreaded architecture is proposed. The proposed architecture saves the energy wasted by removing idle threads without manipulation on the original architecture, fulfills a seamless switching mechanism which protects active threads and avoids pipeline stall during power mode switching. The report of an implemented dynamic multithreaded processor with 45 nm process from synthesis tool indicates that the area of dynamic multithreaded architecture is only 2.27% higher than the static one in achieving dynamic power dissipation, and consumes 1.3% more power in the same peak performance.展开更多
文摘This paper presents the power hardware in the loop(PHIL)validation of a feed forward DC voltage control scheme for the fault ride through(FRT)of voltage source converter(VSC)high voltage DC(HVDC)connected offshore wind power plants(WPPs).In the proposed FRT scheme,the WPP collector network AC voltage is actively controlled by considering both the DC voltage error and the AC current from the WPP AC collector system which ensures fast and robust FRT of the VSC HVDC connected offshore WPPs.The PHIL tests were carried out in order to verify the efficacy of the proposed feed forward DC voltage control scheme for enhancing the FRT capability of the VSC HVDC connected WPPs.The PHIL test results have demonstrated the proper control coordination between the offshore WPP and the WPP side VSC and the efficient FRT of the VSC HVDC connected WPPs.
基金supported in part by the National Basic Research Program of China(973 Program)under Grant 2012CB215105.
文摘There is increasing interest in the evaluation of wind turbine control capabilities for providing grid support.Power hardware in the loop(PHIL)simulation is an advanced method that can be used for studying the interaction of hardware with the power network,as the scaled-down actual wind turbine is connected with a simulated system through an amplifier.Special consideration must be made in the design of the PHIL platform to ensure that the system is stable and yields accurate results.This paper presents a method for stabilizing the PHIL interface and improving the accuracy of PHIL simulation in a real-time application.The method factors in both the power and voltage scaling level,and a phase compensation scheme.It uses the reactive power control capability of the wind turbine inverter to eliminate the phase shift imposed by the feedback current filter.This is accomplished with no negative impact on the dynamic behavior of the wind turbine.The PHIL simulation results demonstrate the effectiveness of the proposed stability analysis method and phase compensation scheme.The strength of the platform is demonstrated by extending the simulation method to wind turbine control validation.
基金supported partially by the National High Technical Research and Development Program of China (863 Program) under Grants No. 2011AA040101, No. 2008AA01Z134the National Natural Science Foundation of China under Grants No. 61003251, No. 61172049, No. 61173150+2 种基金the Doctoral Fund of Ministry of Education of China under Grant No. 20100006110015Beijing Municipal Natural Science Foundation under Grant No. Z111100054011078the 2012 Ladder Plan Project of Beijing Key Laboratory of Knowledge Engineering for Materials Science under Grant No. Z121101002812005
文摘In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time embedded system working in the low workload situation, the energy efficiency of the hardware multithread is discussed and a novel dynamic multithreaded architecture is proposed. The proposed architecture saves the energy wasted by removing idle threads without manipulation on the original architecture, fulfills a seamless switching mechanism which protects active threads and avoids pipeline stall during power mode switching. The report of an implemented dynamic multithreaded processor with 45 nm process from synthesis tool indicates that the area of dynamic multithreaded architecture is only 2.27% higher than the static one in achieving dynamic power dissipation, and consumes 1.3% more power in the same peak performance.
