Simulations of photoresist etching,aerial image,exposure,and post-bake processes are integrated to obtain a photolithography process simulation for microelectromechanical system（MEMS） and integrated circuit（IC） fa...Simulations of photoresist etching,aerial image,exposure,and post-bake processes are integrated to obtain a photolithography process simulation for microelectromechanical system（MEMS） and integrated circuit（IC） fabrication based on three-dimensional （3D） cellular automata（CA）. The simulation results agree well with available experimental results. This indicates that the 3D dynamic CA model for the photoresist etching simulation and the 3D CA model for the post-bake simulation could be useful for the monolithic simulation of various lithography processes. This is determined to be useful for the device-sized fabrication process simulation of IC and MEMS.展开更多
A physical model for simulating overlay metrology employing diffraction based overlay(DBO)principles is built.It can help to optimize the metrology wavelength selection in DBO.Simulation result of DBO metrology with a...A physical model for simulating overlay metrology employing diffraction based overlay(DBO)principles is built.It can help to optimize the metrology wavelength selection in DBO.Simulation result of DBO metrology with a model based on the finite-difference time-domain(FDTD)method is presented.A common case(bottom mark asymmetry)in which error signals are always induced in DBO measurement due to the process imperfection were discussed.The overlay sensitivity of the DBO measurement across the visible illumination spectrum has been performed and compared.After adjusting the model parameters compatible with the actual measurement conditions,the metrology wavelengths which provide the accuracy and robustness of DBO measurement can be optimized.展开更多
With the increased design complexities brought in by applying different Reticle Enhancement Technologies (RETs) in nanometer-scale IC manufacturing process, post-RET sign-off verification is quickly becoming necessary...With the increased design complexities brought in by applying different Reticle Enhancement Technologies (RETs) in nanometer-scale IC manufacturing process, post-RET sign-off verification is quickly becoming necessary. By introducing innovative algorithms for lithographic modeling, silicon imaging and yield problem locating, this paper describes a new methodology of IC manufacturability verification based on Dense Silicon Imaging (DSI). Necessity of imaging based verification is analyzed. Existing post-RET verification methods are reviewed and compared to the new methodology. Due to the greatly improved computational efficiency produced by algorithms such as the ~16*log2N/log2M times faster Specialized FFT, DSI based manufacturability checks on full IC scale, which were impractical for applications before, are now realized. Real verification example has been demonstrated and studied as well.展开更多
文摘Simulations of photoresist etching,aerial image,exposure,and post-bake processes are integrated to obtain a photolithography process simulation for microelectromechanical system（MEMS） and integrated circuit（IC） fabrication based on three-dimensional （3D） cellular automata（CA）. The simulation results agree well with available experimental results. This indicates that the 3D dynamic CA model for the photoresist etching simulation and the 3D CA model for the post-bake simulation could be useful for the monolithic simulation of various lithography processes. This is determined to be useful for the device-sized fabrication process simulation of IC and MEMS.
基金supported by the National Science and Technology Major Project of China (Grant No. 2016ZX02301001)
文摘A physical model for simulating overlay metrology employing diffraction based overlay(DBO)principles is built.It can help to optimize the metrology wavelength selection in DBO.Simulation result of DBO metrology with a model based on the finite-difference time-domain(FDTD)method is presented.A common case(bottom mark asymmetry)in which error signals are always induced in DBO measurement due to the process imperfection were discussed.The overlay sensitivity of the DBO measurement across the visible illumination spectrum has been performed and compared.After adjusting the model parameters compatible with the actual measurement conditions,the metrology wavelengths which provide the accuracy and robustness of DBO measurement can be optimized.
基金the National Natural Science Foundation of China(Grant Nos.60176015 , 90207002) the Hi—Tech R&D(863)Program of China(Grant Nos.2002AA1Z1460 , 2003AA1Z1370).
文摘With the increased design complexities brought in by applying different Reticle Enhancement Technologies (RETs) in nanometer-scale IC manufacturing process, post-RET sign-off verification is quickly becoming necessary. By introducing innovative algorithms for lithographic modeling, silicon imaging and yield problem locating, this paper describes a new methodology of IC manufacturability verification based on Dense Silicon Imaging (DSI). Necessity of imaging based verification is analyzed. Existing post-RET verification methods are reviewed and compared to the new methodology. Due to the greatly improved computational efficiency produced by algorithms such as the ~16*log2N/log2M times faster Specialized FFT, DSI based manufacturability checks on full IC scale, which were impractical for applications before, are now realized. Real verification example has been demonstrated and studied as well.
