This paper presents a single event transient(SET) suppressor circuit,which can suppress the effect of SET in charge pump(CP) on the whole PLL frequency synthesizers,and at the same time it brings little negative effec...This paper presents a single event transient(SET) suppressor circuit,which can suppress the effect of SET in charge pump(CP) on the whole PLL frequency synthesizers,and at the same time it brings little negative effect to the system during normal operation.Because the proposed SET suppressor circuit only includes a resistor,a PMOS and an NMOS device,little area penalty is introduced.By preventing SET propagating from CP to low pass filter(LPF) and VCO when a single event strikes on CP output node,the system shows excellent hardness to SET in CP.Mixed simulations are performed on TCAD workbench.The results show that a single event with an LET at 80 MeV cm 2 /mg can only induce approximately 2.3 mV disturbance on the control voltage of VCO.展开更多
A 35-130 MHz/300-360 MHz phase-locked loop frequency synthesizer for △-∑ analog-to-digital con- verter （ADC） in 65 nm CMOS is presented. The frequency synthesizer can work in low phase-noise mode （300-360 MHz） o...A 35-130 MHz/300-360 MHz phase-locked loop frequency synthesizer for △-∑ analog-to-digital con- verter （ADC） in 65 nm CMOS is presented. The frequency synthesizer can work in low phase-noise mode （300-360 MHz） or in low-power mode （35-130 MHz） to satisfy the ADC＇s requirements. To switch between these two modes, a high frequency GHz LC VCO followed by a divided-by-four frequency divider and a low frequency ring VCO followed by a divided-by-two frequency divider are integrated on-chip. The measured results show that the fre- quency synthesizer achieves a phase-noise of-132 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 1.12 ps with 1.74 mW power consumption from a 1.2 V power supply in low phase-noise mode. In low-power mode, the frequency synthesizer achieves a phase-noise of-112 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 7.23 ps with 0.92 mW power consumption from a 1.2 V power supply.展开更多
基金supported by the Nation Twelfth Five-Year Plan (Grant No.11015131)
文摘This paper presents a single event transient(SET) suppressor circuit,which can suppress the effect of SET in charge pump(CP) on the whole PLL frequency synthesizers,and at the same time it brings little negative effect to the system during normal operation.Because the proposed SET suppressor circuit only includes a resistor,a PMOS and an NMOS device,little area penalty is introduced.By preventing SET propagating from CP to low pass filter(LPF) and VCO when a single event strikes on CP output node,the system shows excellent hardness to SET in CP.Mixed simulations are performed on TCAD workbench.The results show that a single event with an LET at 80 MeV cm 2 /mg can only induce approximately 2.3 mV disturbance on the control voltage of VCO.
文摘A 35-130 MHz/300-360 MHz phase-locked loop frequency synthesizer for △-∑ analog-to-digital con- verter （ADC） in 65 nm CMOS is presented. The frequency synthesizer can work in low phase-noise mode （300-360 MHz） or in low-power mode （35-130 MHz） to satisfy the ADC＇s requirements. To switch between these two modes, a high frequency GHz LC VCO followed by a divided-by-four frequency divider and a low frequency ring VCO followed by a divided-by-two frequency divider are integrated on-chip. The measured results show that the fre- quency synthesizer achieves a phase-noise of-132 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 1.12 ps with 1.74 mW power consumption from a 1.2 V power supply in low phase-noise mode. In low-power mode, the frequency synthesizer achieves a phase-noise of-112 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 7.23 ps with 0.92 mW power consumption from a 1.2 V power supply.
