CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a bri...CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.展开更多
For loops with UV divergences,assuming that the physical contributions of loops from UV regions are insignificant,a UV-free scheme method described by an equation is introduced to derive loop results without UV diverg...For loops with UV divergences,assuming that the physical contributions of loops from UV regions are insignificant,a UV-free scheme method described by an equation is introduced to derive loop results without UV divergences in the calculations,i.e.,a route of the analytic continuation T_(F)→T_(P)besides the traditional route∞-∞in the mathematical structure.This scheme provides a new perspective to an open question of the hierarchy problem of Higgs mass,i.e.,an alternative interpretation without fine-tuning within the standard model.展开更多
Sensorless control of switched reluctance motors(SRMs) often requires a hybrid mode combining low-speed pulse injection methods and high-speed model-based estimation.However,pulse injection causes unwanted audible noi...Sensorless control of switched reluctance motors(SRMs) often requires a hybrid mode combining low-speed pulse injection methods and high-speed model-based estimation.However,pulse injection causes unwanted audible noises and torque ripples.This article proposes an enhanced model-based sensorless approach to extend downwards the speed range in which sensorless control can work without injection.An inertial phase-locked loop (IPLL) based on a stator flux observer is introduced for position estimation.Compared to the conventional phase-locked loop scheme,the IPLL offers a more robust disturbance rejection capability and thus reduces the flux model errors at lower speeds.Experimental results substantiate the feasibility of the extended low-speed operation using the model-based sensorless control approach.展开更多
In renewable power generation systems,ensuring the synchronization of the inverter and the power grid is crucial for the stable operation of grid-connected inverters.Nowadays,the phase-locked loop(PLL)technology has b...In renewable power generation systems,ensuring the synchronization of the inverter and the power grid is crucial for the stable operation of grid-connected inverters.Nowadays,the phase-locked loop(PLL)technology has become a widely used grid synchronization method because of its simple implementation and robustness under various grid conditions.Even though a lot of PLLs have been proposed,an overview and comparative analysis of multiple PLLs can be helpful for practical applications.In addition,the weak grid condition is a great challenge for the system.Therefore,this study first presents an overview of the existing PLLs together with their general structures and basic working principles.Depending on the implementation of the phase detector,the PLL can be divided into three categories:power-based PLL(pPLL),orthogonal-signalgenerator-based PLL(OSG-PLL)and adaptive-filter-based PLL(AF-PLL).Then,from the above classification,seven typical single-phase PLLs are selected for further study.Finally,some test results are given,and a comprehensive evaluation of the selected PLLs under different grid conditions is conducted.展开更多
A fully-differential charge pump（FDCP）with perfect current matching and low output current noise is realized for phase-locked loops（PLLs）.An easily stable common-mode feedback（CMFB）circuit which can handle high ...A fully-differential charge pump（FDCP）with perfect current matching and low output current noise is realized for phase-locked loops（PLLs）.An easily stable common-mode feedback（CMFB）circuit which can handle high input voltage swing is proposed.Current mismatch and current noise contribution from the CMFB circuit is minimized.In order to optimize PLL phase noise,the output current noise of the FDCP is analyzed in detail and calculated with the sampling principle.The calculation result agrees well with the simulation.Based on the noise analysis,many methods to lower output current noise of the FDCP are discussed.The fully-differential charge pump is integrated into a 1–2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18μm process.The measured output reference spur is–64 dBc to–69 dBc.The in-band and out-band phase noise is–95 dBc/Hz at 3 kHz frequency offset and–123 dBc/Hz at 1 MHz frequency offset respectively.展开更多
This paper proposes an area-saving dual-path loop filter（LPF）for low-voltage integrated phase-locked loops（PLLs）.With this LPF,output current of the lowpass-path charge-pump（CP）is B times（B〉1）as great as that...This paper proposes an area-saving dual-path loop filter（LPF）for low-voltage integrated phase-locked loops（PLLs）.With this LPF,output current of the lowpass-path charge-pump（CP）is B times（B〉1）as great as that of the integration-path CP.By adding voltages across these two paths,the zero-capacitance is magnified B times equivalently.As a result,the chip size is greatly reduced.Based on this LPF,a 1.2 V 3.5 GHz-band PLL is fabricated in SMIC 0.18μm RFCMOS technology.Its zero-capacitance is only 1/30 of that in conventional second-order LPFs. Measured data show that,at a frequency of 3.20 GHz,phase noise is–120.2 dBc/Hz at 1 MHz offset,reference spur is–72 dBc,and power is 24 mW.展开更多
This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objec...This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power,jitter and area.An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analyt-ically and benchmarked with respect to their figure-of-merit(FoM).The paper also summarizes the key concerns on the selection of dif-ferent circuit techniques to optimize the clock performance under dif-ferent scenarios.展开更多
A design of a ll. 6-GHz phase-locked loop （PLL） fabricated in 49-GHz 0. 18-μm CMOS （complementary metal-oxide-semiconductor transistor） technology is described. An analog multiplier phase detector （PD）, a one-p...A design of a ll. 6-GHz phase-locked loop （PLL） fabricated in 49-GHz 0. 18-μm CMOS （complementary metal-oxide-semiconductor transistor） technology is described. An analog multiplier phase detector （PD）, a one-pole passive low pass filter and a three-stage ring oscillator with variable negativeresistance loads build up the monolithic phase-locked loop. The measured rms jitter of output signal via onwafer testing is 2. 2 ps under the stimulation of 2^31 - 1 bit-long pseudo random bit sequence （PRBS） at the bit rate of 11.6 GHz. And the tracking range is 250 MHz. The phase noise in the locked condition is measured to be - 107 dBc/Hz at 10 MHz offset, and that of the ring VCO at the central frequency is -99 dBc/Hz at 10 MHz offset. The circuit area of the proposed PLL is only 0. 47mm×0.72mm and the direct current （DC） power dissipation is 164 mW under a 1.8-V supply.展开更多
Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping appro...Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping approach of a slave Raman laser within an optical phase-locked loop(OPLL),which finds practical application in an atomic gravimeter,where the OPLL frequently switches between near-resonance lasers and significantly detuned Raman lasers.The method merges the advantages of rapid and extensive frequency hopping with the OPLL’s inherent low phase noise,and exhibits a versatile range of applications in compact laser systems,promising advancements in portable instruments.展开更多
A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacr...A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.展开更多
There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon...There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.展开更多
We present an ameliorated arctangent algorithm based on phase-locked loop for digital Doppler signal processing,utilized within the heterodyne detection system. We define the error gain factor given by the approximati...We present an ameliorated arctangent algorithm based on phase-locked loop for digital Doppler signal processing,utilized within the heterodyne detection system. We define the error gain factor given by the approximation of Taylor expansion by means of a comparison of the measured values and true values. Exact expressions are derived for the amplitude error of two in-phase & quadrature signals and the frequency error of the acousto-optic modulator. Numerical simulation results and experimental results make it clear that the dynamic instability of the intermediate frequency signals leads to cumulative errors, which will spiral upward. An improved arctangent algorithm for the heterodyne detection is proposed to eliminate the cumulative errors and harmonic components. Depending on the narrow-band filter, our experiments were performed to realize the detectable displacement of 20 nm at a detection distance of 20 m. The aim of this paper is the demonstration of the optimized arctangent algorithm as a powerful approach to the demodulation algorithm, which will advance the signal-to-noise ratio and measurement accuracy of the heterodyne detection system.展开更多
Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to abo...Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.展开更多
High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase...High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase-locked loop(PLL)type filters with respect to ramp speed reference tracking and steady-state performances,as well as the achievement of adaptive cutoff frequency control.An improved LPF-based filter structure with no ramping and steady-state errors caused by filter parameter quantization effects is proposed,which is suitable for applying LPF for sensorless drives of AC machines,especially when fixed-point digital signal processor is selected e.g.in mass production.Furthermore,the potential of adopting PLL for speed filtering is explored.It is demonstrated that PLL type filters can well maintain the advantages offered by the improved LPF.Moreover,it is found that the PLL type filters exhibit almost linear relationship between the cutoff frequency of the PLL filter and its proportional-integral(PI)gains,which can ease the realization of speed filters with adaptive cutoff frequency for improving the speed transient performance.The proposed filters are verified experimentally.The PLL type filter with adaptive cutoff frequency can provide satisfactory performances under various operating conditions and is therefore recommended.展开更多
An extended state observer(ESO)-based loop filter is designed for the phase-locked loop(PLL)involved in a disturbed grid-connected converter(GeC).This ESO-based design enhances the performances and robustness of the P...An extended state observer(ESO)-based loop filter is designed for the phase-locked loop(PLL)involved in a disturbed grid-connected converter(GeC).This ESO-based design enhances the performances and robustness of the PLL,and,therefore,improves control performances of the disturbed GeCs.Besides,the ESO-based LF can be applied to PLLs with extra filters for abnormal grid conditions.The unbalanced grid is particularly taken into account for the performance analysis.A tuning approach based on the well-designed PI controller is discussed,which results in a fair comparison with conventional PI-type PLLs.The frequency domain properies are quantitatively analysed with respeet to the control stability and the noises rejection.The frequency domain analysis and simulation results suggesti that the performances of the generated ESO-based controllers are comparable to those of the PI control at low frequency,while have better ability to atenuate high-frequency measurement noises.The phase margin decreases slightly,but remains acceptable.Finally,experimental tests are conducted with a hybrid power hardwarein-the-loop benchmark,in which balanced/unbalanced cases are both explored.The obtained results prove the effectiveness of ESO based PLLs when applied to the disturbed GeC.展开更多
We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a...We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.展开更多
In this paper,a scheme of commonly-resonated extended interaction circuit system based on high order TMn,mode is proposed to lock the phases of two extended interaction oscillators(EIOs)for generating high power at G-...In this paper,a scheme of commonly-resonated extended interaction circuit system based on high order TMn,mode is proposed to lock the phases of two extended interaction oscillators(EIOs)for generating high power at G-band.Two separate EIOs are coupled through a specific single-gap coupling field supported by a designed gap waveguide with length Lg,which form the phase-locked EIOs based on the commonly-resonated system.As a whole system,the system has been focused on with mode analysis based on different single-gap coupling fields,mode hopping,which present the variation of phase difference between the two-beam-wave interactions when changing Lg.To demonstrate the effectiveness of the proposed circuit system in producing the phase locking,we conducted particle-in-cell(PIC)simulations to show that the interesting mode hopping occurs with the phase difference of O and r between the output signals from two output ports,corresponding to the excitation of the TMn mode with different n.Simulation results show that 1)the oscillator can deliver two times of the output power obtained from one single oscillator at 220 GHz,2)the two EIOs can still deliver output signals with phase difference of O and when the currents of the two beams are different or the fabrication errors of the two EIO cavities are taken into account.The proposed scheme is promising in extending to phase locking between multiple EIOs,and generating higher power at millimeter-wave and higher frequencies.展开更多
This paper discusses the chaos and bifurcation for equation x+cosxx+asinx =ebsint. By use of the Melnikov method the conditions to have the chaotic behavior and to have subharmonic oscillations are given.
基金supported by the Pioneer Hundred Talents Program,Chinese Academy of Sciences.
文摘CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.
基金supported by the open project of the theoretical physics academic exchange platform of Chongqing University。
文摘For loops with UV divergences,assuming that the physical contributions of loops from UV regions are insignificant,a UV-free scheme method described by an equation is introduced to derive loop results without UV divergences in the calculations,i.e.,a route of the analytic continuation T_(F)→T_(P)besides the traditional route∞-∞in the mathematical structure.This scheme provides a new perspective to an open question of the hierarchy problem of Higgs mass,i.e.,an alternative interpretation without fine-tuning within the standard model.
基金supported in part by the National Natural Science Foundation of China 52307069in part by 2024 Tertiary Education Scientific Research Project of Guangzhou Municipal Education Bureau under Grant2024312176in part by the Project of Hetao Shenzhen-Hong Kong Science and Technology Innovation Cooperation Zone under Grant HZQB-KCZYB-2020083。
文摘Sensorless control of switched reluctance motors(SRMs) often requires a hybrid mode combining low-speed pulse injection methods and high-speed model-based estimation.However,pulse injection causes unwanted audible noises and torque ripples.This article proposes an enhanced model-based sensorless approach to extend downwards the speed range in which sensorless control can work without injection.An inertial phase-locked loop (IPLL) based on a stator flux observer is introduced for position estimation.Compared to the conventional phase-locked loop scheme,the IPLL offers a more robust disturbance rejection capability and thus reduces the flux model errors at lower speeds.Experimental results substantiate the feasibility of the extended low-speed operation using the model-based sensorless control approach.
基金This work is supported in part by the National Natural Science Foundation of China(No.51807089,51877104)in part by the Natural Science Foundation of Jiangsu Province(No.BK20180432).
文摘In renewable power generation systems,ensuring the synchronization of the inverter and the power grid is crucial for the stable operation of grid-connected inverters.Nowadays,the phase-locked loop(PLL)technology has become a widely used grid synchronization method because of its simple implementation and robustness under various grid conditions.Even though a lot of PLLs have been proposed,an overview and comparative analysis of multiple PLLs can be helpful for practical applications.In addition,the weak grid condition is a great challenge for the system.Therefore,this study first presents an overview of the existing PLLs together with their general structures and basic working principles.Depending on the implementation of the phase detector,the PLL can be divided into three categories:power-based PLL(pPLL),orthogonal-signalgenerator-based PLL(OSG-PLL)and adaptive-filter-based PLL(AF-PLL).Then,from the above classification,seven typical single-phase PLLs are selected for further study.Finally,some test results are given,and a comprehensive evaluation of the selected PLLs under different grid conditions is conducted.
基金supported by the National High Technology Research and Development Program of China(No.2007AA01Z282)the National Natural Science Foundation of China(No.60876019)
文摘A fully-differential charge pump（FDCP）with perfect current matching and low output current noise is realized for phase-locked loops（PLLs）.An easily stable common-mode feedback（CMFB）circuit which can handle high input voltage swing is proposed.Current mismatch and current noise contribution from the CMFB circuit is minimized.In order to optimize PLL phase noise,the output current noise of the FDCP is analyzed in detail and calculated with the sampling principle.The calculation result agrees well with the simulation.Based on the noise analysis,many methods to lower output current noise of the FDCP are discussed.The fully-differential charge pump is integrated into a 1–2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18μm process.The measured output reference spur is–64 dBc to–69 dBc.The in-band and out-band phase noise is–95 dBc/Hz at 3 kHz frequency offset and–123 dBc/Hz at 1 MHz frequency offset respectively.
文摘This paper proposes an area-saving dual-path loop filter（LPF）for low-voltage integrated phase-locked loops（PLLs）.With this LPF,output current of the lowpass-path charge-pump（CP）is B times（B〉1）as great as that of the integration-path CP.By adding voltages across these two paths,the zero-capacitance is magnified B times equivalently.As a result,the chip size is greatly reduced.Based on this LPF,a 1.2 V 3.5 GHz-band PLL is fabricated in SMIC 0.18μm RFCMOS technology.Its zero-capacitance is only 1/30 of that in conventional second-order LPFs. Measured data show that,at a frequency of 3.20 GHz,phase noise is–120.2 dBc/Hz at 1 MHz offset,reference spur is–72 dBc,and power is 24 mW.
基金supported by the National Natural Science Foundation of China under Grant 62004028,62090041the Science Foundation of Sichuan under Grant 2022NSFSC0927.
文摘This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power,jitter and area.An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analyt-ically and benchmarked with respect to their figure-of-merit(FoM).The paper also summarizes the key concerns on the selection of dif-ferent circuit techniques to optimize the clock performance under dif-ferent scenarios.
基金The National High Technology Research and Devel-opment Program of China (863Program) (No2001AA312010)
文摘A design of a ll. 6-GHz phase-locked loop （PLL） fabricated in 49-GHz 0. 18-μm CMOS （complementary metal-oxide-semiconductor transistor） technology is described. An analog multiplier phase detector （PD）, a one-pole passive low pass filter and a three-stage ring oscillator with variable negativeresistance loads build up the monolithic phase-locked loop. The measured rms jitter of output signal via onwafer testing is 2. 2 ps under the stimulation of 2^31 - 1 bit-long pseudo random bit sequence （PRBS） at the bit rate of 11.6 GHz. And the tracking range is 250 MHz. The phase noise in the locked condition is measured to be - 107 dBc/Hz at 10 MHz offset, and that of the ring VCO at the central frequency is -99 dBc/Hz at 10 MHz offset. The circuit area of the proposed PLL is only 0. 47mm×0.72mm and the direct current （DC） power dissipation is 164 mW under a 1.8-V supply.
基金Project supported by the National Key Research and Development Program of China(Grant Nos.2021YFA0718300 and 2021YFA1400900)the National Natural Science Foundation of China(Grant Nos.11920101004,11934002,and 92365208)+1 种基金Science and Technology Major Project of Shanxi(Grant No.202101030201022)Space Application System of China Manned Space Program.
文摘Raman lasers are essential in atomic physics,and the development of portable devices has posed requirements for time-division multiplexing of Raman lasers.We demonstrate an innovative gigahertz frequency hopping approach of a slave Raman laser within an optical phase-locked loop(OPLL),which finds practical application in an atomic gravimeter,where the OPLL frequently switches between near-resonance lasers and significantly detuned Raman lasers.The method merges the advantages of rapid and extensive frequency hopping with the OPLL’s inherent low phase noise,and exhibits a versatile range of applications in compact laser systems,promising advancements in portable instruments.
文摘A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.
基金supported in part by the National Natural Science Foundation of China(Nos.12005245,12075100,and 11775244)by the Scientific and Technological Innovation Project(No.2020000165)from the Institute of High Energy Physics,Chinese Academy of Sciences+1 种基金partially funded by the Scientific Instrument Development Project of the Chinese Academy of Sciences(No.ZDKYYQ20200007)Youth Innovation Promotion Association of the Chinese Academy of Sciences(No.Y201905).
文摘There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.
基金supported by Key Research Program of Frontier Science,Chinese Academy of Sciences(Grant No.QYZDB-SSW-SLH014)the Yong Scientists Fund of the National Natural Science Foundation of China(Grant No.61205143)
文摘We present an ameliorated arctangent algorithm based on phase-locked loop for digital Doppler signal processing,utilized within the heterodyne detection system. We define the error gain factor given by the approximation of Taylor expansion by means of a comparison of the measured values and true values. Exact expressions are derived for the amplitude error of two in-phase & quadrature signals and the frequency error of the acousto-optic modulator. Numerical simulation results and experimental results make it clear that the dynamic instability of the intermediate frequency signals leads to cumulative errors, which will spiral upward. An improved arctangent algorithm for the heterodyne detection is proposed to eliminate the cumulative errors and harmonic components. Depending on the narrow-band filter, our experiments were performed to realize the detectable displacement of 20 nm at a detection distance of 20 m. The aim of this paper is the demonstration of the optimized arctangent algorithm as a powerful approach to the demodulation algorithm, which will advance the signal-to-noise ratio and measurement accuracy of the heterodyne detection system.
基金Supported by the Tsinghua National Laboratory for Information Science and Technology(TNList)Cross-Discipline Foundationthe National Science and Technology Major Project(No.2010ZX03006-003-01)
文摘Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.
基金This work was supported in part by Lodam A/S and in part by the PSO-ELFORSK Program。
文摘High quality speed information is one of the key issues in machine sensorless drives,which often requires proper filtering of the estimated speed.This paper comparatively studies typical low-pass filters(LPF)and phase-locked loop(PLL)type filters with respect to ramp speed reference tracking and steady-state performances,as well as the achievement of adaptive cutoff frequency control.An improved LPF-based filter structure with no ramping and steady-state errors caused by filter parameter quantization effects is proposed,which is suitable for applying LPF for sensorless drives of AC machines,especially when fixed-point digital signal processor is selected e.g.in mass production.Furthermore,the potential of adopting PLL for speed filtering is explored.It is demonstrated that PLL type filters can well maintain the advantages offered by the improved LPF.Moreover,it is found that the PLL type filters exhibit almost linear relationship between the cutoff frequency of the PLL filter and its proportional-integral(PI)gains,which can ease the realization of speed filters with adaptive cutoff frequency for improving the speed transient performance.The proposed filters are verified experimentally.The PLL type filter with adaptive cutoff frequency can provide satisfactory performances under various operating conditions and is therefore recommended.
基金This paper was supported by G2elab,Grenoble INP,University Grenoble Alpes,France and School of Engineering,HES-sO,Valais,Switzerlandfunding provided by Haute Ecole Specialisee de Suisse occidentale(HES-SO)
文摘An extended state observer(ESO)-based loop filter is designed for the phase-locked loop(PLL)involved in a disturbed grid-connected converter(GeC).This ESO-based design enhances the performances and robustness of the PLL,and,therefore,improves control performances of the disturbed GeCs.Besides,the ESO-based LF can be applied to PLLs with extra filters for abnormal grid conditions.The unbalanced grid is particularly taken into account for the performance analysis.A tuning approach based on the well-designed PI controller is discussed,which results in a fair comparison with conventional PI-type PLLs.The frequency domain properies are quantitatively analysed with respeet to the control stability and the noises rejection.The frequency domain analysis and simulation results suggesti that the performances of the generated ESO-based controllers are comparable to those of the PI control at low frequency,while have better ability to atenuate high-frequency measurement noises.The phase margin decreases slightly,but remains acceptable.Finally,experimental tests are conducted with a hybrid power hardwarein-the-loop benchmark,in which balanced/unbalanced cases are both explored.The obtained results prove the effectiveness of ESO based PLLs when applied to the disturbed GeC.
基金supported by the National Natural Science Foundation of China(Grant No.61307128)the National Basic Research Program of China(GrantNo.2010CB327505)+1 种基金the Specialized Research Found for the Doctoral Program of Higher Education of China(Grant No.20131101120027)the Basic Research Foundation of Beijing Institute of Technology of China(Grant No.20120542015)
文摘We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.
基金Supported in part by the National Natural Science Foundation of China(62401125)the Natural Science Foundation of Sichuan Province(2023NSFSC1376)the Fundamental Research Funds for the Central Universities(ZYGX2024J008)。
文摘In this paper,a scheme of commonly-resonated extended interaction circuit system based on high order TMn,mode is proposed to lock the phases of two extended interaction oscillators(EIOs)for generating high power at G-band.Two separate EIOs are coupled through a specific single-gap coupling field supported by a designed gap waveguide with length Lg,which form the phase-locked EIOs based on the commonly-resonated system.As a whole system,the system has been focused on with mode analysis based on different single-gap coupling fields,mode hopping,which present the variation of phase difference between the two-beam-wave interactions when changing Lg.To demonstrate the effectiveness of the proposed circuit system in producing the phase locking,we conducted particle-in-cell(PIC)simulations to show that the interesting mode hopping occurs with the phase difference of O and r between the output signals from two output ports,corresponding to the excitation of the TMn mode with different n.Simulation results show that 1)the oscillator can deliver two times of the output power obtained from one single oscillator at 220 GHz,2)the two EIOs can still deliver output signals with phase difference of O and when the currents of the two beams are different or the fabrication errors of the two EIO cavities are taken into account.The proposed scheme is promising in extending to phase locking between multiple EIOs,and generating higher power at millimeter-wave and higher frequencies.
基金Project Supported by the National Natural Science Foundation of China
文摘This paper discusses the chaos and bifurcation for equation x+cosxx+asinx =ebsint. By use of the Melnikov method the conditions to have the chaotic behavior and to have subharmonic oscillations are given.
