A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short...A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.展开更多
We propose an in-situ method to calibrate the coil constants of the optical atomic magnetomete. This method is based on measuring the Larmor precession of spin polarized alkali metal atoms and has been demonstrated on...We propose an in-situ method to calibrate the coil constants of the optical atomic magnetomete. This method is based on measuring the Larmor precession of spin polarized alkali metal atoms and has been demonstrated on a K-Rb hybrid atomic magnetomete. Oscillation fields of different frequencies are swept on the transverse coil. By extracting the resonance frequency through phase-frequency analysis of electron spin projection, the coil constants are calibrated to be 323.1±0.28 nT/mA, 108±0.04nT/Ma, and 185.8±1.03 nT/mA along the X,Y, and Z directions, respectively.展开更多
Two essential blocks for the PLLs based on CP, a phase-frequency detector （PFD） and an improved current steering charge-pump （CP）, are developed. The mechanisms for widening the phase error detection range and eli...Two essential blocks for the PLLs based on CP, a phase-frequency detector （PFD） and an improved current steering charge-pump （CP）, are developed. The mechanisms for widening the phase error detection range and eliminating the dead zone are analyzed and applied in our design to optimize the proposed PFD. To obtain excellent current matching and minimum current variation over a wide output voltage range, an improved structure for the proposed CP is developed by fully utilizing many additional sub-circuits. Implemented in a standard 90-nm CMOS process, the proposed PFD achieves a phase error detection range from -354° to 354° and the improved CP demonstrates a current mismatch of less than 1.1% and a pump-current variation of 4% across the output voltage, swinging from 0.2 to 1.1 V, and the power consumption is 1.3 mW under a 1.2-V supply.展开更多
In this article a new achievement of fractional-order 3×n Fan networks is presented.In the first step,the RT-I method is used to derive the general formulae of the equivalent impedance of fractional-order 3×...In this article a new achievement of fractional-order 3×n Fan networks is presented.In the first step,the RT-I method is used to derive the general formulae of the equivalent impedance of fractional-order 3×n Fan networks.In the second part,the effects of five system parameters(L,C,n,α and β)on amplitude-frequency and phase-frequency characteristics are analyzed.At the same time,the amplitude-frequency and phase-frequency characteristics of the fractional order 3×n Fan network are revealed by Matlab drawing.This work has important theoretical and practical significance for resistor network models in the field of natural science and engineering technology.展开更多
A digital phase-locked loop （DPLL） based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works...A digital phase-locked loop （DPLL） based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works from 60 to 600MHz at a supply voltage of 1.8V. It also features a fraetional-N synthesizer with digital 2nd-order sigma-delta noise shaping, which can achieve a short lock time,a high frequency resolution,and an improved phase-noise spectrum. The DPLL has been implemented in SMIC 0. 18μm 1.8V 1P6M CMOS technology. The peak-to-peak jitter is less than 0. 8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider.展开更多
文摘A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.
基金support of the National Key R&D Program of China (Grant No. 2017YFB0503100)the National Natural Science Foundation of China (NSFC)(Grant No. 61227902).
文摘We propose an in-situ method to calibrate the coil constants of the optical atomic magnetomete. This method is based on measuring the Larmor precession of spin polarized alkali metal atoms and has been demonstrated on a K-Rb hybrid atomic magnetomete. Oscillation fields of different frequencies are swept on the transverse coil. By extracting the resonance frequency through phase-frequency analysis of electron spin projection, the coil constants are calibrated to be 323.1±0.28 nT/mA, 108±0.04nT/Ma, and 185.8±1.03 nT/mA along the X,Y, and Z directions, respectively.
基金Project supported by the National Basic Research Program of China(No.2010CB327404)the National High Technology Research and Development Program(No.2011AA10305)the National Natural Science Foundation of China(No.60901012)
文摘Two essential blocks for the PLLs based on CP, a phase-frequency detector （PFD） and an improved current steering charge-pump （CP）, are developed. The mechanisms for widening the phase error detection range and eliminating the dead zone are analyzed and applied in our design to optimize the proposed PFD. To obtain excellent current matching and minimum current variation over a wide output voltage range, an improved structure for the proposed CP is developed by fully utilizing many additional sub-circuits. Implemented in a standard 90-nm CMOS process, the proposed PFD achieves a phase error detection range from -354° to 354° and the improved CP demonstrates a current mismatch of less than 1.1% and a pump-current variation of 4% across the output voltage, swinging from 0.2 to 1.1 V, and the power consumption is 1.3 mW under a 1.2-V supply.
基金supported by the National Training Programs of Innovation and Entrepreneurship for Undergraduates(Grant No.202210304006Z).
文摘In this article a new achievement of fractional-order 3×n Fan networks is presented.In the first step,the RT-I method is used to derive the general formulae of the equivalent impedance of fractional-order 3×n Fan networks.In the second part,the effects of five system parameters(L,C,n,α and β)on amplitude-frequency and phase-frequency characteristics are analyzed.At the same time,the amplitude-frequency and phase-frequency characteristics of the fractional order 3×n Fan network are revealed by Matlab drawing.This work has important theoretical and practical significance for resistor network models in the field of natural science and engineering technology.
文摘A digital phase-locked loop （DPLL） based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works from 60 to 600MHz at a supply voltage of 1.8V. It also features a fraetional-N synthesizer with digital 2nd-order sigma-delta noise shaping, which can achieve a short lock time,a high frequency resolution,and an improved phase-noise spectrum. The DPLL has been implemented in SMIC 0. 18μm 1.8V 1P6M CMOS technology. The peak-to-peak jitter is less than 0. 8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider.
