Persistent memory(PM)allows file systems to directly persist data on the memory bus.To increase the capacity of PM file systems,building a file system across sockets with each attached PM is attractive.However,accessi...Persistent memory(PM)allows file systems to directly persist data on the memory bus.To increase the capacity of PM file systems,building a file system across sockets with each attached PM is attractive.However,accessing data across sockets incurs impacts of the non-uniform memory access(NUMA)architecture,which will lead to significant performance degradation.In this paper,we first use experiments to understand the NUMA impacts on building PM file systems.And then,we propose four design principles for building a high-performance PM file system NapFS for the NUMA architecture.We architect NapFS with per-socket local PM file systems and per-socket dedicated IO thread pools.This not only allows applications to delegate data accesses to IO threads for avoiding remote PM accesses,but also fully reuses existing single-socket PM file systems to reduce implementation complexity.Additionally,NapFS utilizes fast DRAM to accelerate performance by adding a global cache and adopts a selective cache mechanism to eliminate the redundant double-copy overhead for synchronization operations.Lastly,we show that NapFS can adopt extended optimizations to improve scalability and the performance of critical requests.We evaluate NapFS against other multi-socket PM file systems.The evaluation results show that NapFS achieves 2.2x and 1.0x throughput improvement for Filebench and RocksDB,respectively.展开更多
Persistent indexing structures are proposed in response to emerging non-volatile memory(NVM)to provide high performance yet durable indexes.However,due to the lack of real NVM hardware,many prior persistent indexing s...Persistent indexing structures are proposed in response to emerging non-volatile memory(NVM)to provide high performance yet durable indexes.However,due to the lack of real NVM hardware,many prior persistent indexing structures were evaluated via emulation,which varies a lot across different setups and differs from the real deployment.Recently,Intel has released its Optane DC Persistent Memory Module(PMM),which is the first production-ready NVM.In this paper,we revisit popular persistent indexing structures on PMM and conduct comprehensive evaluations to study the performance differences among persistent indexing structures,including persistent hash tables and persistent trees.According to the evaluation results,we find that Cacheline-Conscious Extendible Hashing(CCEH)achieves the best performance among all evaluated persistent hash tables,and Failure-Atomic ShifT B+-Tree(FAST)and Write Optimal Radix Tree(WORT)perform better than other trees.Besides,we find that the insertion performance of hash tables is heavily influenced by data locality,while the insertion latency of trees is dominated by the flush instructions.We also uncover that no existing emulation methods accurately simulate PMM for all the studied data structures.Finally,we provide three suggestions on how to fully utilize PMM for better performance,including using clflushopt/clwb with sfence instead of clflush,flushing continuous data in a batch,and avoiding data access immediately after it is flushed to PMM.展开更多
Emerging persistent memory technologies,like PCM and 3D XPoint,offer numerous advantages,such as higher density,larger capacity,and better energy efficiency,compared with the DRAM.However,they also have some drawbacks...Emerging persistent memory technologies,like PCM and 3D XPoint,offer numerous advantages,such as higher density,larger capacity,and better energy efficiency,compared with the DRAM.However,they also have some drawbacks,e.g.,slower access speed,limited write endurance,and unbalanced read/write latency.Persistent memory technologies provide both great opportunities and challenges for operating systems.As a result,a large number of solutions have been proposed.With the increasing number and complexity of problems and approaches,we believe this is the right moment to investigate and analyze these works systematically.To this end,we perform a comprehensive and in-depth study on operating system support for persistent memory within three steps.First,we present an overview of how to build the operating system on persistent memory from three perspectives:system abstraction,crash consistency,and system reliability.Then,we classify the existing research works into three categories:storage stack,memory manager,and OS-bypassing library.For each category,we summarize the major research topics and discuss these topics deeply.Specifically,we present the challenges and opportunities in each topic,describe the contributions and limitations of proposed approaches,and compare these solutions in different dimensions.Finally,we also envision the future operating system based on this study.展开更多
Emergence of new hardware,including persistent memory and smart network interface card(SmartNIC),has brought new opportunities to file system design.In this paper,we design and implement a new file system named NICFS ...Emergence of new hardware,including persistent memory and smart network interface card(SmartNIC),has brought new opportunities to file system design.In this paper,we design and implement a new file system named NICFS based on persistent memory and SmartNIC.We divide the file system into two parts:the front end and the back end.In the front end,data writes are appended to the persistent memory in a log-structured way,leveraging the fast persistence advantage of persistent memory.In the back end,the data in logs are fetched,processed,and patched to files in the background,leveraging the processing capacity of SmartNIC.Evaluation results show that NICFS outperforms Ext4 by about 21%/10%and about 19%/50%on large and small reads/writes,respectively.展开更多
Persistent memory(PM)file systems have been developed to achieve high performance by exploiting the advanced features of PMs,including nonvolatility,byte addressability,and dynamic random access memory(DRAM)like perfo...Persistent memory(PM)file systems have been developed to achieve high performance by exploiting the advanced features of PMs,including nonvolatility,byte addressability,and dynamic random access memory(DRAM)like performance.Unfortunately,these PMs suffer from limited write endurance.Existing space management strategies of PM file systems can induce a severely unbalanced wear problem,which can damage the underlying PMs quickly.In this paper,we propose a Wear-leveling-aware Multi-grained Allocator,called WMAlloc,to achieve the wear leveling of PMs while improving the performance of file systems.WMAlloc adopts multiple min-heaps to manage the unused space of PMs.Each heap represents an allocation granularity.Then,WMAlloc allocates less-worn blocks from the corresponding min-heap for allocation requests.Moreover,to avoid recursive split and inefficient heap locations in WMAlloc,we further propose a bitmap-based multi-heap tree(BMT)to enhance WMAlloc,namely,WMAlloc-BMT.We implement WMAlloc and WMAlloc-BMT in the Linux kernel based on NOVA,a typical PM file system.Experimental results show that,compared with the original NOVA and dynamic wear-aware range management(DWARM),which is the state-of-the-art wear-leveling-aware allocator of PM file systems,WMAlloc can,respectively,achieve 4.11×and 1.81×maximum write number reduction and 1.02×and 1.64×performance with four workloads on average.Furthermore,WMAlloc-BMT outperforms WMAlloc with 1.08×performance and achieves 1.17×maximum write number reduction with four workloads on average.展开更多
Due to its low latency,byte-addressable,non-volatile,and high density,persistent memory(PM)is expected to be used to design a high-performance storage system.However,PM also has disadvantages such as limited endurance...Due to its low latency,byte-addressable,non-volatile,and high density,persistent memory(PM)is expected to be used to design a high-performance storage system.However,PM also has disadvantages such as limited endurance,thereby proposing challenges to traditional index technologies such as B(+)tree.B(+)tree is originally designed for dynamic random access memory(DRAM)-based or disk-based systems and has a large write amplification problem.The high write amplification is detrimental to a PM-based system.This paper proposes WO-tree,a write-optimized B(+)tree for PM.WO-tree adopts an unordered write mechanism for the leaf nodes,and the unordered write mechanism can reduce a large number of write operations caused by maintaining the entry order in the leaf nodes.When the leaf node is split,WO-tree performs the cache line flushing operation after all write operations are completed,which can reduce frequent data flushing operations.WO-tree adopts a partial logging mechanism and it only writes the log for the leaf node.The inner node recognizes the data inconsistency by the read operation and the data can be recovered using the leaf node information,thereby significantly reducing the logging overhead.Furthermore,WO-tree adopts a lock-free search for inner nodes,which reduces the locking overhead for concurrency operation.We evaluate WO-tree using the Yahoo!Cloud Serving Benchmark(YCSB)workloads.Compared with traditional B(+)tree,wB-tree,and Fast-Fair,the number of cache line flushes caused by WO-tree insertion operations is reduced by 84.7%,22.2%,and 30.8%,respectively,and the execution time is reduced by 84.3%,27.3%,and 44.7%,respectively.展开更多
Byte-addressable non-volatile memory(NVM),as a new participant in the storage hierarchy,gives extremely high performance in storage,which forces changes to be made on current filesystem designs.Page cache,once a signi...Byte-addressable non-volatile memory(NVM),as a new participant in the storage hierarchy,gives extremely high performance in storage,which forces changes to be made on current filesystem designs.Page cache,once a significant mechanism filling the performance gap between Dynamic Random Access Memory(DRAM)and block devices,is now a liability that heavily hinders the writing performance of NVM filesystems.Therefore state-of-the-art NVM filesystems leverage the direct access(DAX)technology to bypass the page cache entirely.However,the DRAM still provides higher bandwidth than NVM,which prevents skewed read workloads from benefiting from a higher bandwidth of the DRAM and leads to sub-optimal performance for the system.In this paper,we propose RCache,a readintensive workload-aware page cache for NVM filesystems.Different from traditional caching mechanisms where all reads go through DRAM,RCache uses a tiered page cache design,including assigning DRAM and NVM to hot and cold data separately,and reading data from both sides.To avoid copying data to DRAM in a critical path,RCache migrates data from NVM to DRAM in a background thread.Additionally,RCache manages data in DRAM in a lock-free manner for better latency and scalability.Evaluations on Intel Optane Data Center(DC)Persistent Memory Modules show that,compared with NOVA,RCache achieves 3 times higher bandwidth for read-intensive workloads and introduces little performance loss for write operations.展开更多
The challenges of power consumption and memory capacity of computers have driven rapid development on non-volatile memories(NVM).NVMs are generally faster than traditional secondary storage devices,write persistently ...The challenges of power consumption and memory capacity of computers have driven rapid development on non-volatile memories(NVM).NVMs are generally faster than traditional secondary storage devices,write persistently and many offer byte addressing capability.Despite these appealing features,NVMs are difficult to manage and program,which makes it hard to use them as a drop-in replacement for dynamic random-access memory(DRAM).Instead,a majority of modern systems use NVMs through the IO and the file system abstractions.Hiding NVMs under these interfaces poses challenges on how to exploit the new hardware’s performance potential in the existing system software framework.In this article,we survey the key technical issues arisen in this area and introduce several recently developed systems each of which offers novel solutions around these issues.展开更多
Non-Volatile Main Memories (NVMMs) have recently emerged as a promising technology for future memory systems. Generally, NVMMs have many desirable properties such as high density, byte-addressability, non-volatility, ...Non-Volatile Main Memories (NVMMs) have recently emerged as a promising technology for future memory systems. Generally, NVMMs have many desirable properties such as high density, byte-addressability, non-volatility, low cost, and energy efficiency, at the expense of high write latency, high write power consumption, and limited write endurance. NVMMs have become a competitive alternative of Dynamic Random Access Memory (DRAM), and will fundamentally change the landscape of memory systems. They bring many research opportunities as well as challenges on system architectural designs, memory management in operating systems (OSes), and programming models for hybrid memory systems. In this article, we revisit the landscape of emerging NVMM technologies, and then survey the state-of-the-art studies of NVMM technologies. We classify those studies with a taxonomy according to different dimensions such as memory architectures, data persistence, performance improvement, energy saving, and wear leveling. Second, to demonstrate the best practices in building NVMM systems, we introduce our recent work of hybrid memory system designs from the dimensions of architectures, systems, and applications. At last, we present our vision of future research directions of NVMMs and shed some light on design challenges and opportunities.展开更多
Persistent memory(PM)promises byte-addressability,large capacity,and durability.Main memory systems,such as key-value stores and in-memory databases,benefit from such features of PM.Due to the great popularity of hash...Persistent memory(PM)promises byte-addressability,large capacity,and durability.Main memory systems,such as key-value stores and in-memory databases,benefit from such features of PM.Due to the great popularity of hash-ing index in main memory systems,a number of research efforts are made to provide high average performance persistent hashing.However,suboptimal tail performance in terms of tail throughput and tail latency is still observed for existing persistent hashing.In this paper,we analyze major sources of suboptimal tail performance from key design issues of persis-tent hashing.We identify the global hash structure and concurrency control as remaining explorable design spaces for im-proving tail performance.We propose Directory-sharing Multi-level Extendible Hashing(Dalea)for PM.Dalea designs an-cestor link-based extendible hashing as well as fine-grained transient lock to address the two main sources(rehashing and locking)affecting tail performance.The evaluation results show that,compared with state-of-the-art persistent hashing Dash,Dalea achieves increased tail throughput by 4.1x and reduced tail latency by 5.4x.Moreover,in order to provide de-sign guidelines for improving tail performance,we adopt Dalea as a testbed to identify different impacts of four factors on tail performance,including fine-grained rehashing,transient locking,memory pre-allocation,and fingerprinting.展开更多
Emerging byte-addressable non-volatile memory technologies, such as phase change memory （PCM） and spin- transfer torque RAM （STT-RAM）, offer both the byte-addressability of memory and the durability of storage, th...Emerging byte-addressable non-volatile memory technologies, such as phase change memory （PCM） and spin- transfer torque RAM （STT-RAM）, offer both the byte-addressability of memory and the durability of storage, thus making it feasible to build single-level store systems. To ensure the consistency of persistent data structures in the presence of power failures or system crashes, it requires flushing cache lines to persistent memory frequently, thus incurring non-trivial synchronization overhead. To mitigate this issue, we propose two techniques. First, we use non-volatile STT-RAM as scratchpad memory on chip to store recovery information, thereby eliminating synchronization cost in the logging phase due to the avoidance of off-chip logging operations. Second, we present an adaptive synchronization policy based on caching modes in terms of data access patterns, thereby eliminating unnecessary synchronization cost in the checkpoint phase. Evaluation results indicate that the two techniques improve the overall performance from 2.15x to 2.39x compared with conventional transactional persistent memory.展开更多
基金supported by the Major Research Plan of the National Natural Science Foundation of China under Grant No.92270202the Strategic Priority Research Program of the Chinese Academy of Sciences under Grant No.XDB44030200.
文摘Persistent memory(PM)allows file systems to directly persist data on the memory bus.To increase the capacity of PM file systems,building a file system across sockets with each attached PM is attractive.However,accessing data across sockets incurs impacts of the non-uniform memory access(NUMA)architecture,which will lead to significant performance degradation.In this paper,we first use experiments to understand the NUMA impacts on building PM file systems.And then,we propose four design principles for building a high-performance PM file system NapFS for the NUMA architecture.We architect NapFS with per-socket local PM file systems and per-socket dedicated IO thread pools.This not only allows applications to delegate data accesses to IO threads for avoiding remote PM accesses,but also fully reuses existing single-socket PM file systems to reduce implementation complexity.Additionally,NapFS utilizes fast DRAM to accelerate performance by adding a global cache and adopts a selective cache mechanism to eliminate the redundant double-copy overhead for synchronization operations.Lastly,we show that NapFS can adopt extended optimizations to improve scalability and the performance of critical requests.We evaluate NapFS against other multi-socket PM file systems.The evaluation results show that NapFS achieves 2.2x and 1.0x throughput improvement for Filebench and RocksDB,respectively.
基金This work is supported in part by the National Key Research and Development Program under Grant No. 2016YFB1000104the National Natural Science Foundation of China under Grant No. 61672345the HighTech Support Program from Shanghai Committee of Science and Technology under Grant No. 19511121100.
文摘Persistent indexing structures are proposed in response to emerging non-volatile memory(NVM)to provide high performance yet durable indexes.However,due to the lack of real NVM hardware,many prior persistent indexing structures were evaluated via emulation,which varies a lot across different setups and differs from the real deployment.Recently,Intel has released its Optane DC Persistent Memory Module(PMM),which is the first production-ready NVM.In this paper,we revisit popular persistent indexing structures on PMM and conduct comprehensive evaluations to study the performance differences among persistent indexing structures,including persistent hash tables and persistent trees.According to the evaluation results,we find that Cacheline-Conscious Extendible Hashing(CCEH)achieves the best performance among all evaluated persistent hash tables,and Failure-Atomic ShifT B+-Tree(FAST)and Write Optimal Radix Tree(WORT)perform better than other trees.Besides,we find that the insertion performance of hash tables is heavily influenced by data locality,while the insertion latency of trees is dominated by the flush instructions.We also uncover that no existing emulation methods accurately simulate PMM for all the studied data structures.Finally,we provide three suggestions on how to fully utilize PMM for better performance,including using clflushopt/clwb with sfence instead of clflush,flushing continuous data in a batch,and avoiding data access immediately after it is flushed to PMM.
基金This work was supported by the Key Technology Improvement of Industrial Control System granted by the Ministry of Industry and Information.
文摘Emerging persistent memory technologies,like PCM and 3D XPoint,offer numerous advantages,such as higher density,larger capacity,and better energy efficiency,compared with the DRAM.However,they also have some drawbacks,e.g.,slower access speed,limited write endurance,and unbalanced read/write latency.Persistent memory technologies provide both great opportunities and challenges for operating systems.As a result,a large number of solutions have been proposed.With the increasing number and complexity of problems and approaches,we believe this is the right moment to investigate and analyze these works systematically.To this end,we perform a comprehensive and in-depth study on operating system support for persistent memory within three steps.First,we present an overview of how to build the operating system on persistent memory from three perspectives:system abstraction,crash consistency,and system reliability.Then,we classify the existing research works into three categories:storage stack,memory manager,and OS-bypassing library.For each category,we summarize the major research topics and discuss these topics deeply.Specifically,we present the challenges and opportunities in each topic,describe the contributions and limitations of proposed approaches,and compare these solutions in different dimensions.Finally,we also envision the future operating system based on this study.
基金Project supported by the National Key R&D Program of China(No.2021YFB0300500)the National Natural Science Foundation of China(No.62022051)。
文摘Emergence of new hardware,including persistent memory and smart network interface card(SmartNIC),has brought new opportunities to file system design.In this paper,we design and implement a new file system named NICFS based on persistent memory and SmartNIC.We divide the file system into two parts:the front end and the back end.In the front end,data writes are appended to the persistent memory in a log-structured way,leveraging the fast persistence advantage of persistent memory.In the back end,the data in logs are fetched,processed,and patched to files in the background,leveraging the processing capacity of SmartNIC.Evaluation results show that NICFS outperforms Ext4 by about 21%/10%and about 19%/50%on large and small reads/writes,respectively.
基金Project supported by the National Natural Science Foundation of China(No.62162011)the Doctor Funds of Guizhou University,China(Nos.2020(13)and 2022(44))。
文摘Persistent memory(PM)file systems have been developed to achieve high performance by exploiting the advanced features of PMs,including nonvolatility,byte addressability,and dynamic random access memory(DRAM)like performance.Unfortunately,these PMs suffer from limited write endurance.Existing space management strategies of PM file systems can induce a severely unbalanced wear problem,which can damage the underlying PMs quickly.In this paper,we propose a Wear-leveling-aware Multi-grained Allocator,called WMAlloc,to achieve the wear leveling of PMs while improving the performance of file systems.WMAlloc adopts multiple min-heaps to manage the unused space of PMs.Each heap represents an allocation granularity.Then,WMAlloc allocates less-worn blocks from the corresponding min-heap for allocation requests.Moreover,to avoid recursive split and inefficient heap locations in WMAlloc,we further propose a bitmap-based multi-heap tree(BMT)to enhance WMAlloc,namely,WMAlloc-BMT.We implement WMAlloc and WMAlloc-BMT in the Linux kernel based on NOVA,a typical PM file system.Experimental results show that,compared with the original NOVA and dynamic wear-aware range management(DWARM),which is the state-of-the-art wear-leveling-aware allocator of PM file systems,WMAlloc can,respectively,achieve 4.11×and 1.81×maximum write number reduction and 1.02×and 1.64×performance with four workloads on average.Furthermore,WMAlloc-BMT outperforms WMAlloc with 1.08×performance and achieves 1.17×maximum write number reduction with four workloads on average.
基金supported in part by the National Natural Science Foundation of China under Grant Nos.U1709220,U2001203,61821003,61872413,and 61902137in part by the National Key Research and Development Program of China under Grant No.2018YFB1003305in part by the Key-Area Research and Development Program of Guangdong Province of China under Grant No.2019B010107001.
文摘Due to its low latency,byte-addressable,non-volatile,and high density,persistent memory(PM)is expected to be used to design a high-performance storage system.However,PM also has disadvantages such as limited endurance,thereby proposing challenges to traditional index technologies such as B(+)tree.B(+)tree is originally designed for dynamic random access memory(DRAM)-based or disk-based systems and has a large write amplification problem.The high write amplification is detrimental to a PM-based system.This paper proposes WO-tree,a write-optimized B(+)tree for PM.WO-tree adopts an unordered write mechanism for the leaf nodes,and the unordered write mechanism can reduce a large number of write operations caused by maintaining the entry order in the leaf nodes.When the leaf node is split,WO-tree performs the cache line flushing operation after all write operations are completed,which can reduce frequent data flushing operations.WO-tree adopts a partial logging mechanism and it only writes the log for the leaf node.The inner node recognizes the data inconsistency by the read operation and the data can be recovered using the leaf node information,thereby significantly reducing the logging overhead.Furthermore,WO-tree adopts a lock-free search for inner nodes,which reduces the locking overhead for concurrency operation.We evaluate WO-tree using the Yahoo!Cloud Serving Benchmark(YCSB)workloads.Compared with traditional B(+)tree,wB-tree,and Fast-Fair,the number of cache line flushes caused by WO-tree insertion operations is reduced by 84.7%,22.2%,and 30.8%,respectively,and the execution time is reduced by 84.3%,27.3%,and 44.7%,respectively.
基金supported by ZTE Industry⁃University⁃Institute Coopera⁃tion Funds under Grant No.HC⁃CN⁃20181128026.
文摘Byte-addressable non-volatile memory(NVM),as a new participant in the storage hierarchy,gives extremely high performance in storage,which forces changes to be made on current filesystem designs.Page cache,once a significant mechanism filling the performance gap between Dynamic Random Access Memory(DRAM)and block devices,is now a liability that heavily hinders the writing performance of NVM filesystems.Therefore state-of-the-art NVM filesystems leverage the direct access(DAX)technology to bypass the page cache entirely.However,the DRAM still provides higher bandwidth than NVM,which prevents skewed read workloads from benefiting from a higher bandwidth of the DRAM and leads to sub-optimal performance for the system.In this paper,we propose RCache,a readintensive workload-aware page cache for NVM filesystems.Different from traditional caching mechanisms where all reads go through DRAM,RCache uses a tiered page cache design,including assigning DRAM and NVM to hot and cold data separately,and reading data from both sides.To avoid copying data to DRAM in a critical path,RCache migrates data from NVM to DRAM in a background thread.Additionally,RCache manages data in DRAM in a lock-free manner for better latency and scalability.Evaluations on Intel Optane Data Center(DC)Persistent Memory Modules show that,compared with NOVA,RCache achieves 3 times higher bandwidth for read-intensive workloads and introduces little performance loss for write operations.
文摘The challenges of power consumption and memory capacity of computers have driven rapid development on non-volatile memories(NVM).NVMs are generally faster than traditional secondary storage devices,write persistently and many offer byte addressing capability.Despite these appealing features,NVMs are difficult to manage and program,which makes it hard to use them as a drop-in replacement for dynamic random-access memory(DRAM).Instead,a majority of modern systems use NVMs through the IO and the file system abstractions.Hiding NVMs under these interfaces poses challenges on how to exploit the new hardware’s performance potential in the existing system software framework.In this article,we survey the key technical issues arisen in this area and introduce several recently developed systems each of which offers novel solutions around these issues.
基金Supported jointly by the National Natural Science Foundation of China under Grants Nos. 61672251, 61732010, 61825202, and 61929103.
文摘Non-Volatile Main Memories (NVMMs) have recently emerged as a promising technology for future memory systems. Generally, NVMMs have many desirable properties such as high density, byte-addressability, non-volatility, low cost, and energy efficiency, at the expense of high write latency, high write power consumption, and limited write endurance. NVMMs have become a competitive alternative of Dynamic Random Access Memory (DRAM), and will fundamentally change the landscape of memory systems. They bring many research opportunities as well as challenges on system architectural designs, memory management in operating systems (OSes), and programming models for hybrid memory systems. In this article, we revisit the landscape of emerging NVMM technologies, and then survey the state-of-the-art studies of NVMM technologies. We classify those studies with a taxonomy according to different dimensions such as memory architectures, data persistence, performance improvement, energy saving, and wear leveling. Second, to demonstrate the best practices in building NVMM systems, we introduce our recent work of hybrid memory system designs from the dimensions of architectures, systems, and applications. At last, we present our vision of future research directions of NVMMs and shed some light on design challenges and opportunities.
基金supported by the Strategic Priority Research Program of the Chinese Academy of Sciences under Grant No.XDB44030200the Beijing Natural Science Foundation-Haidian Joint Fund for Original Innovation under Grant No.L192038.
文摘Persistent memory(PM)promises byte-addressability,large capacity,and durability.Main memory systems,such as key-value stores and in-memory databases,benefit from such features of PM.Due to the great popularity of hash-ing index in main memory systems,a number of research efforts are made to provide high average performance persistent hashing.However,suboptimal tail performance in terms of tail throughput and tail latency is still observed for existing persistent hashing.In this paper,we analyze major sources of suboptimal tail performance from key design issues of persis-tent hashing.We identify the global hash structure and concurrency control as remaining explorable design spaces for im-proving tail performance.We propose Directory-sharing Multi-level Extendible Hashing(Dalea)for PM.Dalea designs an-cestor link-based extendible hashing as well as fine-grained transient lock to address the two main sources(rehashing and locking)affecting tail performance.The evaluation results show that,compared with state-of-the-art persistent hashing Dash,Dalea achieves increased tail throughput by 4.1x and reduced tail latency by 5.4x.Moreover,in order to provide de-sign guidelines for improving tail performance,we adopt Dalea as a testbed to identify different impacts of four factors on tail performance,including fine-grained rehashing,transient locking,memory pre-allocation,and fingerprinting.
基金This work was supported by the National Natural Science Foundation of China under Grant Nos. 61502321, 61472260, and 61402302, the Beijing Natural Science Foundation under Grant No. 4143060, the Overseas Visiting Scholar Program of Beijing under Grant No. 067135300100, the State Key Laboratory of Computer Architecture of China under Grant No. CARCH201503, and the Beijing Innovative Teams and Teacher Career Development Program under Grant No. IDHT20150507.
文摘Emerging byte-addressable non-volatile memory technologies, such as phase change memory （PCM） and spin- transfer torque RAM （STT-RAM）, offer both the byte-addressability of memory and the durability of storage, thus making it feasible to build single-level store systems. To ensure the consistency of persistent data structures in the presence of power failures or system crashes, it requires flushing cache lines to persistent memory frequently, thus incurring non-trivial synchronization overhead. To mitigate this issue, we propose two techniques. First, we use non-volatile STT-RAM as scratchpad memory on chip to store recovery information, thereby eliminating synchronization cost in the logging phase due to the avoidance of off-chip logging operations. Second, we present an adaptive synchronization policy based on caching modes in terms of data access patterns, thereby eliminating unnecessary synchronization cost in the checkpoint phase. Evaluation results indicate that the two techniques improve the overall performance from 2.15x to 2.39x compared with conventional transactional persistent memory.
