Nonlinearity caused by the clock feed-through of a bootstrapped switch and its compensation techniques are analyzed. All kinds of clock feed-through compensation configurations and their drawbacks are also investigate...Nonlinearity caused by the clock feed-through of a bootstrapped switch and its compensation techniques are analyzed. All kinds of clock feed-through compensation configurations and their drawbacks are also investigated. It is pointed out that the delay path match of the clock boosting circuit is the critical factor that affects the effectiveness of clock feed-through compensation. Based on that, a new clock feed-through compensation configuration and corresponding bootstrapped switch are presented and designed optimally with the UMC mixed-mode/RF 0.18 μm 1P6M P-sub twin-well CMOS process by orientating and elaborately designing the switch MOSFETs that influence the delay path match of the clock boosting circuit. HSPICE simulation results show that the proposed clock feedthrough compensation configuration can not only enhance the sampling accuracy under variations of process, power supply voltage, temperature and capacitors but also decrease the even harmonic, high-order odd harmonic and THD on the whole effectively.展开更多
基金supported by the National Natural Science Foundation of China(No.60206006)the New Century Excellent Talents of Ministry of Education of China(No.NCET-05-0851)+1 种基金the Cultivation Fund of the Key Scientific and Technical Innovation Project,Ministry of Education of China Program(No.708083)the Applied Materials Innovation Fund(No.XA-AM-200701)
文摘Nonlinearity caused by the clock feed-through of a bootstrapped switch and its compensation techniques are analyzed. All kinds of clock feed-through compensation configurations and their drawbacks are also investigated. It is pointed out that the delay path match of the clock boosting circuit is the critical factor that affects the effectiveness of clock feed-through compensation. Based on that, a new clock feed-through compensation configuration and corresponding bootstrapped switch are presented and designed optimally with the UMC mixed-mode/RF 0.18 μm 1P6M P-sub twin-well CMOS process by orientating and elaborately designing the switch MOSFETs that influence the delay path match of the clock boosting circuit. HSPICE simulation results show that the proposed clock feedthrough compensation configuration can not only enhance the sampling accuracy under variations of process, power supply voltage, temperature and capacitors but also decrease the even harmonic, high-order odd harmonic and THD on the whole effectively.
