Software-defined satellite networks(SDSNs)play an essential role in future networks.Due to the diverse service scenarios,SDSN faces the demand of packet processing for heterogeneous protocols.Existing packet switching...Software-defined satellite networks(SDSNs)play an essential role in future networks.Due to the diverse service scenarios,SDSN faces the demand of packet processing for heterogeneous protocols.Existing packet switching typically works on one single protocol.For protocol-heterogeneous users,existing packet switch architectures have to construct multiple protocol-specific switching instances,resulting in severe resource waste.In this article,we propose the heterogeneous protocol-independent packet switch architecture(HISA).HISA employs a fast parsing structure to achieve efficient heterogeneous packet parsing and a novel match-action pipeline to achieve shared packet processing among heterogeneous users.HISA can also support the online configuration of switching behaviors.Use cases illustrate the effectiveness of applying HISA in SDSN.Numerical results show that compared to existing packet switching,HISA can significantly improve the resource utilization of SDSN.展开更多
The demands of programmability have become more and more exigent as novel network services appear, such as E-commerce, social softwares, and online videos. Commodity multi-core CPUs have been widely applied in network...The demands of programmability have become more and more exigent as novel network services appear, such as E-commerce, social softwares, and online videos. Commodity multi-core CPUs have been widely applied in network packet processing to get high programmability and reduce the time-to-market. However,there is a great gap between the packet processing performance of commodity multi-core and that of the traditional packet processing hardware, e.g., NP(Network Process). Recently, optimization of the packet processing performance of commodity multi-cores has become a hot topic in industry and academia. In this paper, based on a detailed analysis of the packet processing procedure, firstly we identify two dominating overheads, namely the virtual-to-physical address translation and the packet buffer management. Secondly, we make a comprehensive survey on the current optimization methods. Thirdly, based on the survey, the heterogeneous architecture of the commodity multi-core + FPGA is proposed as a promising way to improve the packet processing performance.Fourthly, a novel Self-Described Buffer(SDB) management technology is introduced to eliminate the overheads of the allocation and deallocation of the packet buffers offloaded to FPGA. Then, an evaluation testbed, named PIOT(Packet I/O Testbed), is designed and implemented to evaluate the packet forwarding performance. I/O capacity of different commodity multi-core CPUs and the performance of optimization methods are assessed and compared based on PIOT. At last, the future work of packet processing optimization on multi-core CPUs is discussed.展开更多
We express a photonic packet switch prototype based on optical label processing methods which dramatically increase the label processing capability. We experimentally demonstrate 40Gbit/s/port packet switching and opt...We express a photonic packet switch prototype based on optical label processing methods which dramatically increase the label processing capability. We experimentally demonstrate 40Gbit/s/port packet switching and optical buffering capabilities of the prototype.展开更多
基金supported by the National Natural Science Foundation of China(62101300,62341130)the Youth Fund Program of the Beijing National Research Center for Information Science and Technology under Grant BNR2021RC01012the Open Research Fund Program of the Beijing National Research Center for Information Science and Technology under Grant BNR2021KF02001.
文摘Software-defined satellite networks(SDSNs)play an essential role in future networks.Due to the diverse service scenarios,SDSN faces the demand of packet processing for heterogeneous protocols.Existing packet switching typically works on one single protocol.For protocol-heterogeneous users,existing packet switch architectures have to construct multiple protocol-specific switching instances,resulting in severe resource waste.In this article,we propose the heterogeneous protocol-independent packet switch architecture(HISA).HISA employs a fast parsing structure to achieve efficient heterogeneous packet parsing and a novel match-action pipeline to achieve shared packet processing among heterogeneous users.HISA can also support the online configuration of switching behaviors.Use cases illustrate the effectiveness of applying HISA in SDSN.Numerical results show that compared to existing packet switching,HISA can significantly improve the resource utilization of SDSN.
基金supported by National High-tech R&D Program of China(863 Program)(Grant No.2015AA0156-03)National Natural Science Foundation of China(Grant No.61202483)
文摘The demands of programmability have become more and more exigent as novel network services appear, such as E-commerce, social softwares, and online videos. Commodity multi-core CPUs have been widely applied in network packet processing to get high programmability and reduce the time-to-market. However,there is a great gap between the packet processing performance of commodity multi-core and that of the traditional packet processing hardware, e.g., NP(Network Process). Recently, optimization of the packet processing performance of commodity multi-cores has become a hot topic in industry and academia. In this paper, based on a detailed analysis of the packet processing procedure, firstly we identify two dominating overheads, namely the virtual-to-physical address translation and the packet buffer management. Secondly, we make a comprehensive survey on the current optimization methods. Thirdly, based on the survey, the heterogeneous architecture of the commodity multi-core + FPGA is proposed as a promising way to improve the packet processing performance.Fourthly, a novel Self-Described Buffer(SDB) management technology is introduced to eliminate the overheads of the allocation and deallocation of the packet buffers offloaded to FPGA. Then, an evaluation testbed, named PIOT(Packet I/O Testbed), is designed and implemented to evaluate the packet forwarding performance. I/O capacity of different commodity multi-core CPUs and the performance of optimization methods are assessed and compared based on PIOT. At last, the future work of packet processing optimization on multi-core CPUs is discussed.
文摘We express a photonic packet switch prototype based on optical label processing methods which dramatically increase the label processing capability. We experimentally demonstrate 40Gbit/s/port packet switching and optical buffering capabilities of the prototype.
