An on-chip debug circuit based on Joint Test Action Group(JTAG)interface for L-digital signal processor(L-DSP)is proposed,which has debug functions such as storage resource access,central processing unit(CPU)pipeline ...An on-chip debug circuit based on Joint Test Action Group(JTAG)interface for L-digital signal processor(L-DSP)is proposed,which has debug functions such as storage resource access,central processing unit(CPU)pipeline control,hardware breakpoint/observation point,and parameter statistics.Compared with traditional debug mode,the proposed debug circuit completes direct transmission of data between peripherals and memory by adding data test-direct memory access(DT-DMA)module,which improves debug efficiency greatly.The proposed circuit was designed in a 0.18μm complementary metal-oxide-semiconductor(CMOS)process with an area of 167234.76μm~2 and a power consumption of 8.89 mW.And the proposed debug circuit and L-DSP were verified under a field programmable gate array(FPGA).Experimental results show that the proposed circuit has complete debug functions and the rate of DT-DMA for transferring debug data is three times faster than the CPU.展开更多
Microbatteries(MBs)are crucial to power miniaturized devices for the Internet of Things.In the evolutionary journey of MBs,fabrication technology emerges as the cornerstone,guiding the intricacies of their configurati...Microbatteries(MBs)are crucial to power miniaturized devices for the Internet of Things.In the evolutionary journey of MBs,fabrication technology emerges as the cornerstone,guiding the intricacies of their configuration designs,ensuring precision,and facilitating scalability for mass production.Photolithography stands out as an ideal technology,leveraging its unparalleled resolution,exceptional design flexibility,and entrenched position within the mature semiconductor industry.However,comprehensive reviews on its application in MB development remain scarce.This review aims to bridge that gap by thoroughly assessing the recent status and promising prospects of photolithographic microfabrication for MBs.Firstly,we delve into the fundamental principles and step-by-step procedures of photolithography,offering a nuanced understanding of its operational mechanisms and the criteria for photoresist selection.Subsequently,we highlighted the specific roles of photolithography in the fabrication of MBs,including its utilization as a template for creating miniaturized micropatterns,a protective layer during the etching process,a mold for soft lithography,a constituent of MB active component,and a sacrificial layer in the construction of micro-Swiss-roll structure.Finally,the review concludes with a summary of the key challenges and future perspectives of MBs fabricated by photolithography,providing comprehensive insights and sparking research inspiration in this field.展开更多
Coupled-waveguide devices are essential in photonic integrated circuits for coupling,polarization handling,and mode manipulation.However,the performance of these devices usually suffers from high wavelength and struct...Coupled-waveguide devices are essential in photonic integrated circuits for coupling,polarization handling,and mode manipulation.However,the performance of these devices usually suffers from high wavelength and structure sensitivity,which makes it challenging to realize broadband and reliable on-chip optical functions.Recently,topological pumping of edge states has emerged as a promising solution for implementing robust optical couplings.In this paper,we propose and experimentally demonstrate broadband on-chip mode manipulation with very large fabrication tolerance based on the Rice–Mele modeled silicon waveguide arrays.The Thouless pumping mechanism is employed in the design to implement broadband and robust mode conversion and multiplexing.The experimental results prove that various mode-order conversions with low insertion losses and intermodal crosstalk can be achieved over a broad bandwidth of 80 nm ranging from 1500 to 1580 nm.Thanks to such a topological design,the device has a remarkable fabrication tolerance of±70 nm for the structural deviations in waveguide width and gap distance,which is,to the best of our knowledge,the highest among the coupled-waveguide mode-handling devices reported so far.As a proof-of-concept experiment,we cascade the topological mode-order converters to form a four-channel mode-division multiplexer and demonstrate the transmission of a 200-Gb/s 16-quadrature amplitude modulation signal for each mode channel,with the bit error rates below the 7%forward error correction threshold of 3.8×10^(-3).We reveal the possibility of developing new classes of broadband and fabrication-tolerant coupled-waveguide devices with topological photonic approaches,which may find applications in many fields,including optical interconnects,quantum communications,and optical computing.展开更多
A new on-chip light source configuration has been proposed,which utilizes the interaction between a microwave or laser and a dielectric nanopillar array to generate a periodic electromagnetic near-field and applies pe...A new on-chip light source configuration has been proposed,which utilizes the interaction between a microwave or laser and a dielectric nanopillar array to generate a periodic electromagnetic near-field and applies periodic transverse acceleration to relativistic electrons to generate high-energy photon radiation.The dielectric nanopillar array interacting with the driving field acts as an electron undulator,in which the near-field drives electrons to oscillate.When an electron beam propagates through this nanopillar array in this light source configuration,it is subjected to a periodic transverse near-field force and will radiate X-ray or evenγ-ray high-energy photons after a relativistic frequency up-conversion.Compared with the undulator which is based on the interaction between strong lasers and nanostructures to generate a plasmonic near-field,this configuration is less prone to damage during operation.展开更多
On-chip global buses in deep sub-micron designs consume significant amounts of energy and have large propagation delays. Thus, minimizing energy dissipation and propagation delay is an important design objective. In t...On-chip global buses in deep sub-micron designs consume significant amounts of energy and have large propagation delays. Thus, minimizing energy dissipation and propagation delay is an important design objective. In this paper, we propose a new spatial and temporal encoding approach for generic on-chip global buses with repeaters that enables higher performance while reducing peak energy and average energy. The proposed encoding approach exploits the benefits of a temporal encoding circuit and spatial bus-invert coding techniques to simultaneously eliminate opposite transitions on adjacent wires and reduce the number of self-transitions and coupling-transitions. In the design process of applying encoding techniques for reduced bus delay and energy, we present a repeater insertion design methodology to determine the repeater size and inter-repeater bus length, which minimizes the total bus energy dissipation while satisfying target delay and slew-rate constraints. This methodology is employed to obtain optimal energy versus delay trade-offs under slew-rate constraints for various encoding techniques.展开更多
Dual pn junctions in lateral and vertical directions are formed by diffusing the p^＋ on the patterned n-well in standard CMOS technology, which are inserted under the inductor in order to reduce the currents in the s...Dual pn junctions in lateral and vertical directions are formed by diffusing the p^＋ on the patterned n-well in standard CMOS technology, which are inserted under the inductor in order to reduce the currents in the substrate induced by the electromagnetic field from the inductor. The thickness of high resistance is not equivalent to the width of the depletion region of the vertical pn junctions,but the depth of the bottom pn junction in the substrate are both proposed and validated. For the first time, through the grounded p^＋-diffusion layer shielding the suhstrate from the electric field of the inductor, the width of the depletion regions of the lateral and vertical pn junctions are changed by increasing the voltage applied to the n wells. The quality factor is improved or reduced with the thickness of high resistance by 19%. This phenomenon validates the theory that the pn junction substrate isolation can reduce the loss caused by the currents in the substrate induced by the electromagnetic field from the inductor.展开更多
[Objective] The aim was to test the controlling effect of cleaning steriliza- tion system, material conveying system, and fermentation jar cooling system with equip- ments of fruit wine production line introduced in t...[Objective] The aim was to test the controlling effect of cleaning steriliza- tion system, material conveying system, and fermentation jar cooling system with equip- ments of fruit wine production line introduced in this study and its auto-control sys- tem field assembled and debugged. [Method] Based on controlling equipment and setting parameters on the configuration interface, the operation state of the control equipments could be real-time monitored and controlled with the help of configura- tion software. [Result] The result showed that the equipment system could reduce the temperature into 12 ℃ with the error of ＋0.5 ℃within 110 minutes when the fermentation temperature is set at 12 ℃ in real production. [Conclusion] The auto- control system of fruit wine production line was easy to be assembled and de- bugged to meet demands of different fruit wine productions.展开更多
基金supported by the China-Montenegro 3rd Science&Technology Exchange and Cooperation Project(3-7)the Open Research Fund of Hunan Provincial Key Laboratory of Flexible Electronic Materials Genome Engineering(202005)the Double First-Class Scientific Research International Cooperation Expansion Project of Changsha University of Science&Technology(2019ic18)。
文摘An on-chip debug circuit based on Joint Test Action Group(JTAG)interface for L-digital signal processor(L-DSP)is proposed,which has debug functions such as storage resource access,central processing unit(CPU)pipeline control,hardware breakpoint/observation point,and parameter statistics.Compared with traditional debug mode,the proposed debug circuit completes direct transmission of data between peripherals and memory by adding data test-direct memory access(DT-DMA)module,which improves debug efficiency greatly.The proposed circuit was designed in a 0.18μm complementary metal-oxide-semiconductor(CMOS)process with an area of 167234.76μm~2 and a power consumption of 8.89 mW.And the proposed debug circuit and L-DSP were verified under a field programmable gate array(FPGA).Experimental results show that the proposed circuit has complete debug functions and the rate of DT-DMA for transferring debug data is three times faster than the CPU.
基金supported by the National Natural Science Foundation of China(22125903,22439003,22209175)the National Key R&D Program of China(Grant 2022YFA1504100,2023YFB4005204)+1 种基金the Energy Revolution S&T Program of Yulin Innovation Institute of Clean Energy(Grant E412010508)the State Key Laboratory of Catalysis(No:2024SKL-A-001)。
文摘Microbatteries(MBs)are crucial to power miniaturized devices for the Internet of Things.In the evolutionary journey of MBs,fabrication technology emerges as the cornerstone,guiding the intricacies of their configuration designs,ensuring precision,and facilitating scalability for mass production.Photolithography stands out as an ideal technology,leveraging its unparalleled resolution,exceptional design flexibility,and entrenched position within the mature semiconductor industry.However,comprehensive reviews on its application in MB development remain scarce.This review aims to bridge that gap by thoroughly assessing the recent status and promising prospects of photolithographic microfabrication for MBs.Firstly,we delve into the fundamental principles and step-by-step procedures of photolithography,offering a nuanced understanding of its operational mechanisms and the criteria for photoresist selection.Subsequently,we highlighted the specific roles of photolithography in the fabrication of MBs,including its utilization as a template for creating miniaturized micropatterns,a protective layer during the etching process,a mold for soft lithography,a constituent of MB active component,and a sacrificial layer in the construction of micro-Swiss-roll structure.Finally,the review concludes with a summary of the key challenges and future perspectives of MBs fabricated by photolithography,providing comprehensive insights and sparking research inspiration in this field.
基金supported by the National Key R&D Program of China(Grant No.2023YFB2905503)the National Natural Science Foundation of China(Grant Nos.62035016,62105200,62475146,and 62341508).
文摘Coupled-waveguide devices are essential in photonic integrated circuits for coupling,polarization handling,and mode manipulation.However,the performance of these devices usually suffers from high wavelength and structure sensitivity,which makes it challenging to realize broadband and reliable on-chip optical functions.Recently,topological pumping of edge states has emerged as a promising solution for implementing robust optical couplings.In this paper,we propose and experimentally demonstrate broadband on-chip mode manipulation with very large fabrication tolerance based on the Rice–Mele modeled silicon waveguide arrays.The Thouless pumping mechanism is employed in the design to implement broadband and robust mode conversion and multiplexing.The experimental results prove that various mode-order conversions with low insertion losses and intermodal crosstalk can be achieved over a broad bandwidth of 80 nm ranging from 1500 to 1580 nm.Thanks to such a topological design,the device has a remarkable fabrication tolerance of±70 nm for the structural deviations in waveguide width and gap distance,which is,to the best of our knowledge,the highest among the coupled-waveguide mode-handling devices reported so far.As a proof-of-concept experiment,we cascade the topological mode-order converters to form a four-channel mode-division multiplexer and demonstrate the transmission of a 200-Gb/s 16-quadrature amplitude modulation signal for each mode channel,with the bit error rates below the 7%forward error correction threshold of 3.8×10^(-3).We reveal the possibility of developing new classes of broadband and fabrication-tolerant coupled-waveguide devices with topological photonic approaches,which may find applications in many fields,including optical interconnects,quantum communications,and optical computing.
基金pported by the National Natural Science Foundation of China(Grant Nos.12325409,12388102,12074398,and U2267204)the CAS Project for Young Scientists in Basic Research(Grant No.YSBR-060)the Shanghai Pilot Program for Basic Research,Chinese Academy of Sciences Shanghai Branch。
文摘A new on-chip light source configuration has been proposed,which utilizes the interaction between a microwave or laser and a dielectric nanopillar array to generate a periodic electromagnetic near-field and applies periodic transverse acceleration to relativistic electrons to generate high-energy photon radiation.The dielectric nanopillar array interacting with the driving field acts as an electron undulator,in which the near-field drives electrons to oscillate.When an electron beam propagates through this nanopillar array in this light source configuration,it is subjected to a periodic transverse near-field force and will radiate X-ray or evenγ-ray high-energy photons after a relativistic frequency up-conversion.Compared with the undulator which is based on the interaction between strong lasers and nanostructures to generate a plasmonic near-field,this configuration is less prone to damage during operation.
文摘On-chip global buses in deep sub-micron designs consume significant amounts of energy and have large propagation delays. Thus, minimizing energy dissipation and propagation delay is an important design objective. In this paper, we propose a new spatial and temporal encoding approach for generic on-chip global buses with repeaters that enables higher performance while reducing peak energy and average energy. The proposed encoding approach exploits the benefits of a temporal encoding circuit and spatial bus-invert coding techniques to simultaneously eliminate opposite transitions on adjacent wires and reduce the number of self-transitions and coupling-transitions. In the design process of applying encoding techniques for reduced bus delay and energy, we present a repeater insertion design methodology to determine the repeater size and inter-repeater bus length, which minimizes the total bus energy dissipation while satisfying target delay and slew-rate constraints. This methodology is employed to obtain optimal energy versus delay trade-offs under slew-rate constraints for various encoding techniques.
文摘Dual pn junctions in lateral and vertical directions are formed by diffusing the p^＋ on the patterned n-well in standard CMOS technology, which are inserted under the inductor in order to reduce the currents in the substrate induced by the electromagnetic field from the inductor. The thickness of high resistance is not equivalent to the width of the depletion region of the vertical pn junctions,but the depth of the bottom pn junction in the substrate are both proposed and validated. For the first time, through the grounded p^＋-diffusion layer shielding the suhstrate from the electric field of the inductor, the width of the depletion regions of the lateral and vertical pn junctions are changed by increasing the voltage applied to the n wells. The quality factor is improved or reduced with the thickness of high resistance by 19%. This phenomenon validates the theory that the pn junction substrate isolation can reduce the loss caused by the currents in the substrate induced by the electromagnetic field from the inductor.
基金Supported by Fundamental Research Foundation of GXAAS(GNK2013YM02)~~
文摘[Objective] The aim was to test the controlling effect of cleaning steriliza- tion system, material conveying system, and fermentation jar cooling system with equip- ments of fruit wine production line introduced in this study and its auto-control sys- tem field assembled and debugged. [Method] Based on controlling equipment and setting parameters on the configuration interface, the operation state of the control equipments could be real-time monitored and controlled with the help of configura- tion software. [Result] The result showed that the equipment system could reduce the temperature into 12 ℃ with the error of ＋0.5 ℃within 110 minutes when the fermentation temperature is set at 12 ℃ in real production. [Conclusion] The auto- control system of fruit wine production line was easy to be assembled and de- bugged to meet demands of different fruit wine productions.
