Microbatteries(MBs)are crucial to power miniaturized devices for the Internet of Things.In the evolutionary journey of MBs,fabrication technology emerges as the cornerstone,guiding the intricacies of their configurati...Microbatteries(MBs)are crucial to power miniaturized devices for the Internet of Things.In the evolutionary journey of MBs,fabrication technology emerges as the cornerstone,guiding the intricacies of their configuration designs,ensuring precision,and facilitating scalability for mass production.Photolithography stands out as an ideal technology,leveraging its unparalleled resolution,exceptional design flexibility,and entrenched position within the mature semiconductor industry.However,comprehensive reviews on its application in MB development remain scarce.This review aims to bridge that gap by thoroughly assessing the recent status and promising prospects of photolithographic microfabrication for MBs.Firstly,we delve into the fundamental principles and step-by-step procedures of photolithography,offering a nuanced understanding of its operational mechanisms and the criteria for photoresist selection.Subsequently,we highlighted the specific roles of photolithography in the fabrication of MBs,including its utilization as a template for creating miniaturized micropatterns,a protective layer during the etching process,a mold for soft lithography,a constituent of MB active component,and a sacrificial layer in the construction of micro-Swiss-roll structure.Finally,the review concludes with a summary of the key challenges and future perspectives of MBs fabricated by photolithography,providing comprehensive insights and sparking research inspiration in this field.展开更多
Coupled-waveguide devices are essential in photonic integrated circuits for coupling,polarization handling,and mode manipulation.However,the performance of these devices usually suffers from high wavelength and struct...Coupled-waveguide devices are essential in photonic integrated circuits for coupling,polarization handling,and mode manipulation.However,the performance of these devices usually suffers from high wavelength and structure sensitivity,which makes it challenging to realize broadband and reliable on-chip optical functions.Recently,topological pumping of edge states has emerged as a promising solution for implementing robust optical couplings.In this paper,we propose and experimentally demonstrate broadband on-chip mode manipulation with very large fabrication tolerance based on the Rice–Mele modeled silicon waveguide arrays.The Thouless pumping mechanism is employed in the design to implement broadband and robust mode conversion and multiplexing.The experimental results prove that various mode-order conversions with low insertion losses and intermodal crosstalk can be achieved over a broad bandwidth of 80 nm ranging from 1500 to 1580 nm.Thanks to such a topological design,the device has a remarkable fabrication tolerance of±70 nm for the structural deviations in waveguide width and gap distance,which is,to the best of our knowledge,the highest among the coupled-waveguide mode-handling devices reported so far.As a proof-of-concept experiment,we cascade the topological mode-order converters to form a four-channel mode-division multiplexer and demonstrate the transmission of a 200-Gb/s 16-quadrature amplitude modulation signal for each mode channel,with the bit error rates below the 7%forward error correction threshold of 3.8×10^(-3).We reveal the possibility of developing new classes of broadband and fabrication-tolerant coupled-waveguide devices with topological photonic approaches,which may find applications in many fields,including optical interconnects,quantum communications,and optical computing.展开更多
A new on-chip light source configuration has been proposed,which utilizes the interaction between a microwave or laser and a dielectric nanopillar array to generate a periodic electromagnetic near-field and applies pe...A new on-chip light source configuration has been proposed,which utilizes the interaction between a microwave or laser and a dielectric nanopillar array to generate a periodic electromagnetic near-field and applies periodic transverse acceleration to relativistic electrons to generate high-energy photon radiation.The dielectric nanopillar array interacting with the driving field acts as an electron undulator,in which the near-field drives electrons to oscillate.When an electron beam propagates through this nanopillar array in this light source configuration,it is subjected to a periodic transverse near-field force and will radiate X-ray or evenγ-ray high-energy photons after a relativistic frequency up-conversion.Compared with the undulator which is based on the interaction between strong lasers and nanostructures to generate a plasmonic near-field,this configuration is less prone to damage during operation.展开更多
On-chip global buses in deep sub-micron designs consume significant amounts of energy and have large propagation delays. Thus, minimizing energy dissipation and propagation delay is an important design objective. In t...On-chip global buses in deep sub-micron designs consume significant amounts of energy and have large propagation delays. Thus, minimizing energy dissipation and propagation delay is an important design objective. In this paper, we propose a new spatial and temporal encoding approach for generic on-chip global buses with repeaters that enables higher performance while reducing peak energy and average energy. The proposed encoding approach exploits the benefits of a temporal encoding circuit and spatial bus-invert coding techniques to simultaneously eliminate opposite transitions on adjacent wires and reduce the number of self-transitions and coupling-transitions. In the design process of applying encoding techniques for reduced bus delay and energy, we present a repeater insertion design methodology to determine the repeater size and inter-repeater bus length, which minimizes the total bus energy dissipation while satisfying target delay and slew-rate constraints. This methodology is employed to obtain optimal energy versus delay trade-offs under slew-rate constraints for various encoding techniques.展开更多
Dual pn junctions in lateral and vertical directions are formed by diffusing the p^＋ on the patterned n-well in standard CMOS technology, which are inserted under the inductor in order to reduce the currents in the s...Dual pn junctions in lateral and vertical directions are formed by diffusing the p^＋ on the patterned n-well in standard CMOS technology, which are inserted under the inductor in order to reduce the currents in the substrate induced by the electromagnetic field from the inductor. The thickness of high resistance is not equivalent to the width of the depletion region of the vertical pn junctions,but the depth of the bottom pn junction in the substrate are both proposed and validated. For the first time, through the grounded p^＋-diffusion layer shielding the suhstrate from the electric field of the inductor, the width of the depletion regions of the lateral and vertical pn junctions are changed by increasing the voltage applied to the n wells. The quality factor is improved or reduced with the thickness of high resistance by 19%. This phenomenon validates the theory that the pn junction substrate isolation can reduce the loss caused by the currents in the substrate induced by the electromagnetic field from the inductor.展开更多
Gas identification and concentration measurements are important for both understanding and monitoring a variety of phenomena from industrial processes to environmental change.Here a novel mid-IR plasmonic gas sensor w...Gas identification and concentration measurements are important for both understanding and monitoring a variety of phenomena from industrial processes to environmental change.Here a novel mid-IR plasmonic gas sensor with on-chip direct readout is proposed based on unity integration of narrowband spectral response,localized field enhancement and thermal detection.A systematic investigation consisting of both optical and thermal simulations for gas sensing is presented for the first time in three sensing modes including refractive index sensing,absorption sensing and spectroscopy,respectively.It is found that a detection limit less than 100 ppm for CO2 could be realized by a combination of surface plasmon resonance enhancement and metal-organic framework gas enrichment with an enhancement factor over 8000 in an ultracompact optical interaction length of only several microns.Moreover,on-chip spectroscopy is demonstrated with the compressive sensing algorithm via a narrowband plasmonic sensor array.An array of 80 such sensors with an average resonance linewidth of 10 nm reconstructs the CO2 molecular absorption spectrum with the estimated resolution of approximately 0.01 nm far beyond the state-of-the-art spectrometer.The novel device design and analytical method are expected to provide a promising technique for extensive applications of distributed or portable mid-IR gas sensor.展开更多
Design aspects of CMOS compatible on-chip antenna for applications of contact-less smart card are discussed.An on-chip antenna model is established and a design method is demonstrated.Experimental results show that sy...Design aspects of CMOS compatible on-chip antenna for applications of contact-less smart card are discussed.An on-chip antenna model is established and a design method is demonstrated.Experimental results show that system-on-chip integrating power reception together with other electronic functions of smart card applications is feasible.In a 6×10 -4T magnetic field of 22.5MHz,an on-chip power of 1.225mW for a 10kΩ load is obtained using a 4mm2 on-chip antenna.展开更多
A cold preamplifier based on superconducting quantum interference devices(SQUIDs)is currently the preferred readout technology for the low-noise transition edge sensor(TES).In this work,we have designed and fabricated...A cold preamplifier based on superconducting quantum interference devices(SQUIDs)is currently the preferred readout technology for the low-noise transition edge sensor(TES).In this work,we have designed and fabricated a series SQUID array(SSA)amplifier for the TES detector readout circuit.In this SSA amplifier,each SQUID cell is composed of a first-order gradiometer formed using two equally large square washers,and an on-chip low pass filter(LPF)as a radiofrequency(RF)choke has been developed to reduce the Josephson oscillation interference between individual SQUID cells.In addition,a highly symmetric layout has been designed carefully to provide a fully consistent embedded electromagnetic environment and achieve coherent flux operation.The measured results show smooth V-Φcharacteristics and a swing voltage that increases linearly with increasing SQUID cell number N.A white flux noise level as low as 0.28μφ;/Hz;is achieved at 0.1 K,corresponding to a low current noise level of 7 pA/Hz;.We analyze the measured noise contribution at mK-scale temperatures and find that the dominant noise derives from a combination of the SSA intrinsic noise and the equivalent current noise of the room temperature electronics.展开更多
Multidimensional integration and multifunctional com-ponent assembly have been greatly explored in recent years to extend Moore’s Law of modern microelectronics.However,this inevitably exac-erbates the inhomogeneity ...Multidimensional integration and multifunctional com-ponent assembly have been greatly explored in recent years to extend Moore’s Law of modern microelectronics.However,this inevitably exac-erbates the inhomogeneity of temperature distribution in microsystems,making precise temperature control for electronic components extremely challenging.Herein,we report an on-chip micro temperature controller including a pair of thermoelectric legs with a total area of 50×50μm^(2),which are fabricated from dense and flat freestanding Bi2Te3-based ther-moelectric nano films deposited on a newly developed nano graphene oxide membrane substrate.Its tunable equivalent thermal resistance is controlled by electrical currents to achieve energy-efficient temperature control for low-power electronics.A large cooling temperature difference of 44.5 K at 380 K is achieved with a power consumption of only 445μW,resulting in an ultrahigh temperature control capability over 100 K mW^(-1).Moreover,an ultra-fast cooling rate exceeding 2000 K s^(-1) and excellent reliability of up to 1 million cycles are observed.Our proposed on-chip temperature controller is expected to enable further miniaturization and multifunctional integration on a single chip for microelectronics.展开更多
This paper presents a technique for low noise figure reduction of low-noise amplifier (LNA). The proposed LNA is designed in a source degeneration technique that offers lower noise figure. The resistance of the on-chi...This paper presents a technique for low noise figure reduction of low-noise amplifier (LNA). The proposed LNA is designed in a source degeneration technique that offers lower noise figure. The resistance of the on-chip inductor is reduced by using multilayer that significantly reduces the thermal noise due to spiral inductor. Also, using spiral inductor as a gate inductor reduces the effect of the input parasitic capacitance on the noise figure and provides a good matching at the input and output of the LNA. The results of the LNA using multilayer on-chip inductor compared will off-chip inductor have been illustrated. It shows that the proposed technique reduces significantly the noise figure and improves the matching. The proposed LNA is designed in 0.13 μm process with 1.3 V supply voltage and simulated using Advanced Design System (ADS) software. The simulation results show that the LNA is unconditionally stable and provides a forward gain of 11.087 dB at operating frequency of 15 GHz with 1.784 dB noise figure and input and output impedance matching of –17.93 dB, and –10.04 dB.展开更多
Graphene-based electrodes with rational structural design have shown extraordinary prospect for en-hanced electrical double-layer capacitance of micro-supercapacitors(MSCs).Herein,a facile fabrication method for flexi...Graphene-based electrodes with rational structural design have shown extraordinary prospect for en-hanced electrical double-layer capacitance of micro-supercapacitors(MSCs).Herein,a facile fabrication method for flexible planar MSCs based on hierarchical graphene was demonstrated by using a laser-treated membrane for electrode patterning,complemented with hierarchical electrode configuration tak-ing full advantages of size-determined functional graphene.The in-plane interdigital shape of MSCs was defined through vacuum filtration with the assistance of the functionalized polypropylene(PP)mem-brane.The hierarchical graphene films were built by macroscopic assembly based on size effect of differ-ent lateral sized graphene sheets(rGO-LSL).The sample of MSCs based on rGO-L SL(MSCs-LSL)exhibited excellent volumetric capacitance of 6.7 F cm^(−3) and high energy density of 0.37 mWh cm−3.The MSCs-LSL presented superb flexibility and cycling stability with no capacitance deteroriated after 2000 cycles.This newly developed fabrication strategy is of good scalability and designability to manufacture flexible elec-trode for MSCs with customized shapes,while the construction of hierarchical graphene can enlighten the structural design of analogous two-dimensional materials for potential advanced electronics.展开更多
In the complex multicore chip system,network on-chip(NoC)is viewed as a kind of system interconnection that can substitute the traditional interconnect networks,which will improve the system performance and communicat...In the complex multicore chip system,network on-chip(NoC)is viewed as a kind of system interconnection that can substitute the traditional interconnect networks,which will improve the system performance and communication efficiency.With regard to the complex and large scale NoC,simple and efficient routing nodes are the critical factors to achieve low-cost and low-congestion communication performance.This paper proposes an unbuffered switch architecture and makes detailed analysis of the mechanism of buffer in the switch architecture.According to the simulation results,the S-mesh using the unbuffered switch architecture is better in terms of the optimal performance in message latency than some typical NoC architectures,such as 2D-mesh,Fat-tree,Butterfly,Octagon and so on.The synthesis results of design compiler indicate that the unbuffered switch has obvious advantages of achieving cost and operating speed for the chips.展开更多
Capillary electrophoresis (CE) suffers from a relatively small sensitivity—at least in case of optical detection transversely to the capillary axis due to the small capillary inner diameters in the range of 50 - 100 ...Capillary electrophoresis (CE) suffers from a relatively small sensitivity—at least in case of optical detection transversely to the capillary axis due to the small capillary inner diameters in the range of 50 - 100 μm. Different concepts like bubble, U-, or Z-cells have been used to tackle that problem already in the nineties of the last century. But the U- and Z-cells have typically been extra cells with larger inner channel diameters and no optimization for optical waveguiding and the bubble cell per se did not allow for optical waveguiding. In the case of on-chip capillary electrophoresis (chip-CE) a U-cell can be implemented quite easily on the chip. Here we show how leaky optical waveguiding can be employed to improve optical detection. Proper U-channel design and preparation by wet-chemical etching of the fused silica sub- and superstrate, making the U-channel bend a part of the optical input lens system, can help to achieve high coupling efficiency with loss coefficients around 2 dB and low waveguiding loss.展开更多
A single mode hybrid Ⅲ-Ⅴ/silicon on-chip laser based on the flip-chip bonding technology for on-chip optical interconnection is demonstrated. A single mode Fabry-Perot laser structure with micro-structures on an InP...A single mode hybrid Ⅲ-Ⅴ/silicon on-chip laser based on the flip-chip bonding technology for on-chip optical interconnection is demonstrated. A single mode Fabry-Perot laser structure with micro-structures on an InP ridge waveguide is designed and fabricated on an InP/AIGaInAs multiple quantum well epitaxial layer structure wafer by using i-line lithography. Then, a silicon waveguide platform including a laser mounting stage is designed and fabricated on a silicon-on-insulator substrate. The single mode laser is flip-chip bonded on the laser mounting stage. The lasing light is butt-coupling to the silicon waveguide. The laser power output from a silicon waveguide is 1.3roW, and the threshold is 37mA at room temperature and continuous wave operation.展开更多
Integrated photonic devices are essential for on-chip optical communication,optical-electronic systems,and quantum information sciences.To develop a high-fidelity interface between photonics in various frequency domai...Integrated photonic devices are essential for on-chip optical communication,optical-electronic systems,and quantum information sciences.To develop a high-fidelity interface between photonics in various frequency domains without disturbing their quantum properties,nonlinear frequency conversion,typically steered with the quadratic(χ2)process,should be considered.Furthermore,another degree of freedom in steering the spatial modes during theχ2 process,with unprecedent mode intensity is proposed here by modulating the lithium niobate(LN)waveguide-based inter-mode quasi-phasematching conditions with both temperature and wavelength parameters.Under high incident light intensities(25 and 27.8 dBm for the pump and the signal lights,respectively),mode conversion at the sum-frequency wavelength with sufficient high output power(−7–8 dBm)among the TM01,TM10,and TM00 modes is realized automatically with characterized broad temperature(ΔT≥8°C)and wavelength windows(Δλ≥1 nm),avoiding the previous efforts in carefully preparing the signal or pump modes.The results prove that high-intensity spatial modes can be prepared at arbitrary transparent wavelength of theχ2 media toward on-chip integration,which facilitates the development of chip-based communication and quantum information systems because spatial correlations can be applied to generate hyperentangled states and provide additional robustness in quantum error correction with the extended Hilbert space.展开更多
GaN-based devices have developed significantly in recent years due to their promising applications and research potential.A major goal is to monolithically integrate various GaN-based components onto a single chip to ...GaN-based devices have developed significantly in recent years due to their promising applications and research potential.A major goal is to monolithically integrate various GaN-based components onto a single chip to create future optoelectronic systems with low power consumption.This miniaturized integration not only enhances multifunctional performance but also reduces material,processing,and packaging costs.In this study,we present an optoelectronic on-chip system fabricated using a top-down approach on a III-nitride-on-silicon wafer.The system includes a near-ultraviolet light source,a monitor,a 180°bent waveguide,an electro-absorption modulator,and a receiver,all integrated without the need for regrowth or post-growth doping.35 Mbit/s optical data communication is demonstrated through light propagation within the system,confirming its potential for compact GaN-based optoelectronic solutions.展开更多
The rapid development of portable electronic devices has accelerated the advancement of energy storage devices. On-chip microsupercapacitors（MSCs）, as a group of high performance energy storage devices,have remarkab...The rapid development of portable electronic devices has accelerated the advancement of energy storage devices. On-chip microsupercapacitors（MSCs）, as a group of high performance energy storage devices,have remarkable features of miniaturization, high security, and easy integration to build an all-in-one integrated system to meet the request of micro-portable electronic equipments. With the characteristics of high capacities, environmentally friendly and low cost, metal oxides are thought to be ideal candidates for on-chip MSCs. This paper summarizes the recent progress of metal oxides based on-chip MSCs. It starts with the introduction of several common methods for the synthesis of metal oxides nanostructures. The recent developments on the fabrication and electrochemical performance of metal oxides based on-chip MSCs are then highlighted in detail. Finally, the existing challenges and future perspectives of the on-chip MSCs are discussed.展开更多
The on-chip fabrication of a carbon nanoparticle-chitosan composite membrane （i.e. a sorbent membrane or a mixed matrix membrane） using laminar flow-based interfacial deprotonation technology was presented in this p...The on-chip fabrication of a carbon nanoparticle-chitosan composite membrane （i.e. a sorbent membrane or a mixed matrix membrane） using laminar flow-based interfacial deprotonation technology was presented in this paper. In addition, the effects of carbon nanoparticles and reactant flow rates on membrane formation were investigated. Finally, the permeability and adsorption capacities of the membrane were discussed. During fabrication, an acidic chitosan solution and a basic buffer solution that contained carbon nanoparticles were introduced into a microchannel. At the flow interface, a freestanding composite membrane with embedded carbon nanoparticles was formed due to the deprotonation of the chitosan molecules. The membrane growth gradually stopped with time from upstream to downstream and the thickness of the membrane increased rapidly and then slowly along the reactant flow direction. The formation of the membrane was divided into two stages. The average growth rate in the first stage was significantly larger than the average growth rate in the second stage. Carbon nanoparticles in the basic solution acted as nucleating agents and made the membrane formation much easier. As the flow rate of the chitosan solution increased, the averaged membrane thickness and the membrane hydraulic permeability initially increased and then decreased. Because of the addition of carbon nanoparticles, the formed membrane had adsorption abilities. The carbon nanoparticle-chitosan composite membrane that was fabricated in this study could be employed for simultaneous adsorption and dialysis in microdevices in the future.展开更多
Compared with the traditional and inter-chip networks, on-chip networks （NoCs） have enormous wire resources which can be traded for improving other performance requirements. This means that much wider data links can...Compared with the traditional and inter-chip networks, on-chip networks （NoCs） have enormous wire resources which can be traded for improving other performance requirements. This means that much wider data links can be used for NoCs. This paper focuses on the area costs for on-chip routers under four different data-link widths： 8 bits, 16 bits, 128 bits, and 256bits. Firstly, a virtual-channel based on-chip router is introduced. Secondly, the components of the router are implemented by Verilog HDL models and synthesized by Quartus II 4.0 in a FPGA device. Finally, the area costs are analyzed. It can be seen from the results that data-link width has great influence on area costs of buffers and crossbar while has no influence on area costs of arbiter.展开更多
基金supported by the National Natural Science Foundation of China(22125903,22439003,22209175)the National Key R&D Program of China(Grant 2022YFA1504100,2023YFB4005204)+1 种基金the Energy Revolution S&T Program of Yulin Innovation Institute of Clean Energy(Grant E412010508)the State Key Laboratory of Catalysis(No:2024SKL-A-001)。
文摘Microbatteries(MBs)are crucial to power miniaturized devices for the Internet of Things.In the evolutionary journey of MBs,fabrication technology emerges as the cornerstone,guiding the intricacies of their configuration designs,ensuring precision,and facilitating scalability for mass production.Photolithography stands out as an ideal technology,leveraging its unparalleled resolution,exceptional design flexibility,and entrenched position within the mature semiconductor industry.However,comprehensive reviews on its application in MB development remain scarce.This review aims to bridge that gap by thoroughly assessing the recent status and promising prospects of photolithographic microfabrication for MBs.Firstly,we delve into the fundamental principles and step-by-step procedures of photolithography,offering a nuanced understanding of its operational mechanisms and the criteria for photoresist selection.Subsequently,we highlighted the specific roles of photolithography in the fabrication of MBs,including its utilization as a template for creating miniaturized micropatterns,a protective layer during the etching process,a mold for soft lithography,a constituent of MB active component,and a sacrificial layer in the construction of micro-Swiss-roll structure.Finally,the review concludes with a summary of the key challenges and future perspectives of MBs fabricated by photolithography,providing comprehensive insights and sparking research inspiration in this field.
基金supported by the National Key R&D Program of China(Grant No.2023YFB2905503)the National Natural Science Foundation of China(Grant Nos.62035016,62105200,62475146,and 62341508).
文摘Coupled-waveguide devices are essential in photonic integrated circuits for coupling,polarization handling,and mode manipulation.However,the performance of these devices usually suffers from high wavelength and structure sensitivity,which makes it challenging to realize broadband and reliable on-chip optical functions.Recently,topological pumping of edge states has emerged as a promising solution for implementing robust optical couplings.In this paper,we propose and experimentally demonstrate broadband on-chip mode manipulation with very large fabrication tolerance based on the Rice–Mele modeled silicon waveguide arrays.The Thouless pumping mechanism is employed in the design to implement broadband and robust mode conversion and multiplexing.The experimental results prove that various mode-order conversions with low insertion losses and intermodal crosstalk can be achieved over a broad bandwidth of 80 nm ranging from 1500 to 1580 nm.Thanks to such a topological design,the device has a remarkable fabrication tolerance of±70 nm for the structural deviations in waveguide width and gap distance,which is,to the best of our knowledge,the highest among the coupled-waveguide mode-handling devices reported so far.As a proof-of-concept experiment,we cascade the topological mode-order converters to form a four-channel mode-division multiplexer and demonstrate the transmission of a 200-Gb/s 16-quadrature amplitude modulation signal for each mode channel,with the bit error rates below the 7%forward error correction threshold of 3.8×10^(-3).We reveal the possibility of developing new classes of broadband and fabrication-tolerant coupled-waveguide devices with topological photonic approaches,which may find applications in many fields,including optical interconnects,quantum communications,and optical computing.
基金pported by the National Natural Science Foundation of China(Grant Nos.12325409,12388102,12074398,and U2267204)the CAS Project for Young Scientists in Basic Research(Grant No.YSBR-060)the Shanghai Pilot Program for Basic Research,Chinese Academy of Sciences Shanghai Branch。
文摘A new on-chip light source configuration has been proposed,which utilizes the interaction between a microwave or laser and a dielectric nanopillar array to generate a periodic electromagnetic near-field and applies periodic transverse acceleration to relativistic electrons to generate high-energy photon radiation.The dielectric nanopillar array interacting with the driving field acts as an electron undulator,in which the near-field drives electrons to oscillate.When an electron beam propagates through this nanopillar array in this light source configuration,it is subjected to a periodic transverse near-field force and will radiate X-ray or evenγ-ray high-energy photons after a relativistic frequency up-conversion.Compared with the undulator which is based on the interaction between strong lasers and nanostructures to generate a plasmonic near-field,this configuration is less prone to damage during operation.
文摘On-chip global buses in deep sub-micron designs consume significant amounts of energy and have large propagation delays. Thus, minimizing energy dissipation and propagation delay is an important design objective. In this paper, we propose a new spatial and temporal encoding approach for generic on-chip global buses with repeaters that enables higher performance while reducing peak energy and average energy. The proposed encoding approach exploits the benefits of a temporal encoding circuit and spatial bus-invert coding techniques to simultaneously eliminate opposite transitions on adjacent wires and reduce the number of self-transitions and coupling-transitions. In the design process of applying encoding techniques for reduced bus delay and energy, we present a repeater insertion design methodology to determine the repeater size and inter-repeater bus length, which minimizes the total bus energy dissipation while satisfying target delay and slew-rate constraints. This methodology is employed to obtain optimal energy versus delay trade-offs under slew-rate constraints for various encoding techniques.
文摘Dual pn junctions in lateral and vertical directions are formed by diffusing the p^＋ on the patterned n-well in standard CMOS technology, which are inserted under the inductor in order to reduce the currents in the substrate induced by the electromagnetic field from the inductor. The thickness of high resistance is not equivalent to the width of the depletion region of the vertical pn junctions,but the depth of the bottom pn junction in the substrate are both proposed and validated. For the first time, through the grounded p^＋-diffusion layer shielding the suhstrate from the electric field of the inductor, the width of the depletion regions of the lateral and vertical pn junctions are changed by increasing the voltage applied to the n wells. The quality factor is improved or reduced with the thickness of high resistance by 19%. This phenomenon validates the theory that the pn junction substrate isolation can reduce the loss caused by the currents in the substrate induced by the electromagnetic field from the inductor.
基金We are grateful for financial supports from National Key Research and Development Program of China(No.2019YFB2203402)National Natural Science Foundation of China(Nos.11774383,11774099,11874029)+3 种基金Guangdong Science and Technology Program International Cooperation Program(2018A050506039)Guangdong Natural Science Founds for Distinguished Young Scholars(No.2020B151502074),Pearl River Talent Plan Program of Guangdong(No.2019QN01X120)Fundamental Research Funds for the Central Universities,Royal Society Newton Advanced Fellowship(No.NA140301)Key Frontier Scientific Research Program of the Chinese Academy of Sciences(No.QYZDBSSW-JSC014).
文摘Gas identification and concentration measurements are important for both understanding and monitoring a variety of phenomena from industrial processes to environmental change.Here a novel mid-IR plasmonic gas sensor with on-chip direct readout is proposed based on unity integration of narrowband spectral response,localized field enhancement and thermal detection.A systematic investigation consisting of both optical and thermal simulations for gas sensing is presented for the first time in three sensing modes including refractive index sensing,absorption sensing and spectroscopy,respectively.It is found that a detection limit less than 100 ppm for CO2 could be realized by a combination of surface plasmon resonance enhancement and metal-organic framework gas enrichment with an enhancement factor over 8000 in an ultracompact optical interaction length of only several microns.Moreover,on-chip spectroscopy is demonstrated with the compressive sensing algorithm via a narrowband plasmonic sensor array.An array of 80 such sensors with an average resonance linewidth of 10 nm reconstructs the CO2 molecular absorption spectrum with the estimated resolution of approximately 0.01 nm far beyond the state-of-the-art spectrometer.The novel device design and analytical method are expected to provide a promising technique for extensive applications of distributed or portable mid-IR gas sensor.
文摘Design aspects of CMOS compatible on-chip antenna for applications of contact-less smart card are discussed.An on-chip antenna model is established and a design method is demonstrated.Experimental results show that system-on-chip integrating power reception together with other electronic functions of smart card applications is feasible.In a 6×10 -4T magnetic field of 22.5MHz,an on-chip power of 1.225mW for a 10kΩ load is obtained using a 4mm2 on-chip antenna.
基金supported by the National Key Research and Development Program of China(Grant No.2017YFA0304003)。
文摘A cold preamplifier based on superconducting quantum interference devices(SQUIDs)is currently the preferred readout technology for the low-noise transition edge sensor(TES).In this work,we have designed and fabricated a series SQUID array(SSA)amplifier for the TES detector readout circuit.In this SSA amplifier,each SQUID cell is composed of a first-order gradiometer formed using two equally large square washers,and an on-chip low pass filter(LPF)as a radiofrequency(RF)choke has been developed to reduce the Josephson oscillation interference between individual SQUID cells.In addition,a highly symmetric layout has been designed carefully to provide a fully consistent embedded electromagnetic environment and achieve coherent flux operation.The measured results show smooth V-Φcharacteristics and a swing voltage that increases linearly with increasing SQUID cell number N.A white flux noise level as low as 0.28μφ;/Hz;is achieved at 0.1 K,corresponding to a low current noise level of 7 pA/Hz;.We analyze the measured noise contribution at mK-scale temperatures and find that the dominant noise derives from a combination of the SSA intrinsic noise and the equivalent current noise of the room temperature electronics.
基金The authors thank D.Berger,D.Hofmann and C.Kupka in IFW Dresden for helpful technical support.H.R.acknowledges funding from the DFG(Deutsche Forschungsgemeinschaft)within grant number RE3973/1-1.Q.J.,H.R.and K.N.conceived the work.With the support from N.Y.and X.J.,Q.J.and T.G.fabricated the thermoelectric films and conducted the structural and compositional characterizations.Q.J.prepared microchips and fabricated the on-chip micro temperature controllers.Q.J.and N.P.carried out the temperature-dependent material and device performance measurements.Q.J.and H.R.performed the simulation and analytical calculations.Q.J.,H.R.and K.N.wrote the manuscript with input from the other coauthors.All the authors discussed the results and commented on the manuscript.
文摘Multidimensional integration and multifunctional com-ponent assembly have been greatly explored in recent years to extend Moore’s Law of modern microelectronics.However,this inevitably exac-erbates the inhomogeneity of temperature distribution in microsystems,making precise temperature control for electronic components extremely challenging.Herein,we report an on-chip micro temperature controller including a pair of thermoelectric legs with a total area of 50×50μm^(2),which are fabricated from dense and flat freestanding Bi2Te3-based ther-moelectric nano films deposited on a newly developed nano graphene oxide membrane substrate.Its tunable equivalent thermal resistance is controlled by electrical currents to achieve energy-efficient temperature control for low-power electronics.A large cooling temperature difference of 44.5 K at 380 K is achieved with a power consumption of only 445μW,resulting in an ultrahigh temperature control capability over 100 K mW^(-1).Moreover,an ultra-fast cooling rate exceeding 2000 K s^(-1) and excellent reliability of up to 1 million cycles are observed.Our proposed on-chip temperature controller is expected to enable further miniaturization and multifunctional integration on a single chip for microelectronics.
文摘This paper presents a technique for low noise figure reduction of low-noise amplifier (LNA). The proposed LNA is designed in a source degeneration technique that offers lower noise figure. The resistance of the on-chip inductor is reduced by using multilayer that significantly reduces the thermal noise due to spiral inductor. Also, using spiral inductor as a gate inductor reduces the effect of the input parasitic capacitance on the noise figure and provides a good matching at the input and output of the LNA. The results of the LNA using multilayer on-chip inductor compared will off-chip inductor have been illustrated. It shows that the proposed technique reduces significantly the noise figure and improves the matching. The proposed LNA is designed in 0.13 μm process with 1.3 V supply voltage and simulated using Advanced Design System (ADS) software. The simulation results show that the LNA is unconditionally stable and provides a forward gain of 11.087 dB at operating frequency of 15 GHz with 1.784 dB noise figure and input and output impedance matching of –17.93 dB, and –10.04 dB.
基金financially supported by the National Natural Science Foundation of China (No.51975218 and U22A20193)the Natural Science Foundation of Guangdong Province (No.2021A1515010642)+2 种基金the Science and Technology Planning Project of Guangdong Province (No.2021A0505110002)the Fundamental Research Funds for the Central Universities (No.2022ZYGXZR101)the S&T Innovation Projects of Zhuhai City (No.ZH01110405180034PWC).
文摘Graphene-based electrodes with rational structural design have shown extraordinary prospect for en-hanced electrical double-layer capacitance of micro-supercapacitors(MSCs).Herein,a facile fabrication method for flexible planar MSCs based on hierarchical graphene was demonstrated by using a laser-treated membrane for electrode patterning,complemented with hierarchical electrode configuration tak-ing full advantages of size-determined functional graphene.The in-plane interdigital shape of MSCs was defined through vacuum filtration with the assistance of the functionalized polypropylene(PP)mem-brane.The hierarchical graphene films were built by macroscopic assembly based on size effect of differ-ent lateral sized graphene sheets(rGO-LSL).The sample of MSCs based on rGO-L SL(MSCs-LSL)exhibited excellent volumetric capacitance of 6.7 F cm^(−3) and high energy density of 0.37 mWh cm−3.The MSCs-LSL presented superb flexibility and cycling stability with no capacitance deteroriated after 2000 cycles.This newly developed fabrication strategy is of good scalability and designability to manufacture flexible elec-trode for MSCs with customized shapes,while the construction of hierarchical graphene can enlighten the structural design of analogous two-dimensional materials for potential advanced electronics.
基金Supported by the National High Technology Research and Development Program of China(No.2009AA01Z105)the Ministry of EducationIntel Special Foundation for Information Technology(No.MOE-INTEL-08-05)the Postdoctoral Science Foundation of China(No.20080440942,200902432)
文摘In the complex multicore chip system,network on-chip(NoC)is viewed as a kind of system interconnection that can substitute the traditional interconnect networks,which will improve the system performance and communication efficiency.With regard to the complex and large scale NoC,simple and efficient routing nodes are the critical factors to achieve low-cost and low-congestion communication performance.This paper proposes an unbuffered switch architecture and makes detailed analysis of the mechanism of buffer in the switch architecture.According to the simulation results,the S-mesh using the unbuffered switch architecture is better in terms of the optimal performance in message latency than some typical NoC architectures,such as 2D-mesh,Fat-tree,Butterfly,Octagon and so on.The synthesis results of design compiler indicate that the unbuffered switch has obvious advantages of achieving cost and operating speed for the chips.
文摘Capillary electrophoresis (CE) suffers from a relatively small sensitivity—at least in case of optical detection transversely to the capillary axis due to the small capillary inner diameters in the range of 50 - 100 μm. Different concepts like bubble, U-, or Z-cells have been used to tackle that problem already in the nineties of the last century. But the U- and Z-cells have typically been extra cells with larger inner channel diameters and no optimization for optical waveguiding and the bubble cell per se did not allow for optical waveguiding. In the case of on-chip capillary electrophoresis (chip-CE) a U-cell can be implemented quite easily on the chip. Here we show how leaky optical waveguiding can be employed to improve optical detection. Proper U-channel design and preparation by wet-chemical etching of the fused silica sub- and superstrate, making the U-channel bend a part of the optical input lens system, can help to achieve high coupling efficiency with loss coefficients around 2 dB and low waveguiding loss.
基金Supported by the National Basic Research Program of China under Grant No 2012CB933501the National Natural Science Foundation of China under Grant Nos 61307033,61274070,61137003 and 61321063
文摘A single mode hybrid Ⅲ-Ⅴ/silicon on-chip laser based on the flip-chip bonding technology for on-chip optical interconnection is demonstrated. A single mode Fabry-Perot laser structure with micro-structures on an InP ridge waveguide is designed and fabricated on an InP/AIGaInAs multiple quantum well epitaxial layer structure wafer by using i-line lithography. Then, a silicon waveguide platform including a laser mounting stage is designed and fabricated on a silicon-on-insulator substrate. The single mode laser is flip-chip bonded on the laser mounting stage. The lasing light is butt-coupling to the silicon waveguide. The laser power output from a silicon waveguide is 1.3roW, and the threshold is 37mA at room temperature and continuous wave operation.
基金financial supports from National Key Research and Development Program of China(2021YFB3602500)Self-deployment Project of Fujian Science&Technology Innovation Laboratory for Optoelectronic Information of China(2021ZZ101)National Natural Science Foundation of China(Grant Nos.62275247 and 61905246).
文摘Integrated photonic devices are essential for on-chip optical communication,optical-electronic systems,and quantum information sciences.To develop a high-fidelity interface between photonics in various frequency domains without disturbing their quantum properties,nonlinear frequency conversion,typically steered with the quadratic(χ2)process,should be considered.Furthermore,another degree of freedom in steering the spatial modes during theχ2 process,with unprecedent mode intensity is proposed here by modulating the lithium niobate(LN)waveguide-based inter-mode quasi-phasematching conditions with both temperature and wavelength parameters.Under high incident light intensities(25 and 27.8 dBm for the pump and the signal lights,respectively),mode conversion at the sum-frequency wavelength with sufficient high output power(−7–8 dBm)among the TM01,TM10,and TM00 modes is realized automatically with characterized broad temperature(ΔT≥8°C)and wavelength windows(Δλ≥1 nm),avoiding the previous efforts in carefully preparing the signal or pump modes.The results prove that high-intensity spatial modes can be prepared at arbitrary transparent wavelength of theχ2 media toward on-chip integration,which facilitates the development of chip-based communication and quantum information systems because spatial correlations can be applied to generate hyperentangled states and provide additional robustness in quantum error correction with the extended Hilbert space.
基金This work was supported in part by the National Natural Science Founda⁃tion of China under Grant No.U21A20495National Key Research and De⁃velopment Program of China under Grant No.2022YFE0112000High⁃er Education Discipline Innovation Project under Grant No.D17018.
文摘GaN-based devices have developed significantly in recent years due to their promising applications and research potential.A major goal is to monolithically integrate various GaN-based components onto a single chip to create future optoelectronic systems with low power consumption.This miniaturized integration not only enhances multifunctional performance but also reduces material,processing,and packaging costs.In this study,we present an optoelectronic on-chip system fabricated using a top-down approach on a III-nitride-on-silicon wafer.The system includes a near-ultraviolet light source,a monitor,a 180°bent waveguide,an electro-absorption modulator,and a receiver,all integrated without the need for regrowth or post-growth doping.35 Mbit/s optical data communication is demonstrated through light propagation within the system,confirming its potential for compact GaN-based optoelectronic solutions.
基金supported by the National Natural Science Foundation of China(Nos.51672308,61625404)the Beijing Natural Science Foundation(No.4162062)+1 种基金Beijing Municipal Science and Technology Project(No.Z1711000220000)the Key Research Program of Frontiers Sciences,Chinese Academy of Sciences(No.QYZDY-SSW-JSC004)
文摘The rapid development of portable electronic devices has accelerated the advancement of energy storage devices. On-chip microsupercapacitors（MSCs）, as a group of high performance energy storage devices,have remarkable features of miniaturization, high security, and easy integration to build an all-in-one integrated system to meet the request of micro-portable electronic equipments. With the characteristics of high capacities, environmentally friendly and low cost, metal oxides are thought to be ideal candidates for on-chip MSCs. This paper summarizes the recent progress of metal oxides based on-chip MSCs. It starts with the introduction of several common methods for the synthesis of metal oxides nanostructures. The recent developments on the fabrication and electrochemical performance of metal oxides based on-chip MSCs are then highlighted in detail. Finally, the existing challenges and future perspectives of the on-chip MSCs are discussed.
基金supported by the Natural Science Foundation of Anhui Province,China(No.1408085ME96)the Specialized Research Fund for the Doctoral Program of Higher Education of China(No.20133402120033)the Fundamental Research Funds for the Central Universities of China(No.WK2100000001)
文摘The on-chip fabrication of a carbon nanoparticle-chitosan composite membrane （i.e. a sorbent membrane or a mixed matrix membrane） using laminar flow-based interfacial deprotonation technology was presented in this paper. In addition, the effects of carbon nanoparticles and reactant flow rates on membrane formation were investigated. Finally, the permeability and adsorption capacities of the membrane were discussed. During fabrication, an acidic chitosan solution and a basic buffer solution that contained carbon nanoparticles were introduced into a microchannel. At the flow interface, a freestanding composite membrane with embedded carbon nanoparticles was formed due to the deprotonation of the chitosan molecules. The membrane growth gradually stopped with time from upstream to downstream and the thickness of the membrane increased rapidly and then slowly along the reactant flow direction. The formation of the membrane was divided into two stages. The average growth rate in the first stage was significantly larger than the average growth rate in the second stage. Carbon nanoparticles in the basic solution acted as nucleating agents and made the membrane formation much easier. As the flow rate of the chitosan solution increased, the averaged membrane thickness and the membrane hydraulic permeability initially increased and then decreased. Because of the addition of carbon nanoparticles, the formed membrane had adsorption abilities. The carbon nanoparticle-chitosan composite membrane that was fabricated in this study could be employed for simultaneous adsorption and dialysis in microdevices in the future.
文摘Compared with the traditional and inter-chip networks, on-chip networks （NoCs） have enormous wire resources which can be traded for improving other performance requirements. This means that much wider data links can be used for NoCs. This paper focuses on the area costs for on-chip routers under four different data-link widths： 8 bits, 16 bits, 128 bits, and 256bits. Firstly, a virtual-channel based on-chip router is introduced. Secondly, the components of the router are implemented by Verilog HDL models and synthesized by Quartus II 4.0 in a FPGA device. Finally, the area costs are analyzed. It can be seen from the results that data-link width has great influence on area costs of buffers and crossbar while has no influence on area costs of arbiter.
