A CMOS （complementary metal-oxide-semiconductor transistor） low-dropout regulator （LDO） with 3. 3 V output voltage and 100 mA output current for system-on-chip applications to reduce board space and external pins ...A CMOS （complementary metal-oxide-semiconductor transistor） low-dropout regulator （LDO） with 3. 3 V output voltage and 100 mA output current for system-on-chip applications to reduce board space and external pins is presented. By utilizing a dynamic slew-rate enhancement（SRE） circuit and nested Miller compensation （NMC） on the LDO structure, the proposed LDO provides high stability during line and load regulation without off-chip load capacitors. The overshot voltage is limited within 550 mV and the settling time is less than 50 μs when the load current decreases from 100 mA to 1 mA. By using a 30 nA reference current, the quiescent current is 3.3 μA. The proposed design is implemented by CSMC 0. 5 μm mixed-signal process. The experimental results agree with the simulation results.展开更多
Memristive neural network has attracted tremendous attention since the memristor array can perform parallel multiplyaccumulate calculation(MAC)operations and memory-computation operations as compared with digital CMOS...Memristive neural network has attracted tremendous attention since the memristor array can perform parallel multiplyaccumulate calculation(MAC)operations and memory-computation operations as compared with digital CMOS hardware systems.However,owing to the variability of the memristor,the implementation of high-precision neural network in memristive computation units is still difficult.Existing learning algorithms for memristive artificial neural network(ANN)is unable to achieve the performance comparable to high-precision by using CMOS-based system.Here,we propose an algorithm based on off-chip learning for memristive ANN in low precision.Training the ANN in the high-precision in digital CPUs and then quantifying the weight of the network to low precision,the quantified weights are mapped to the memristor arrays based on VTEAM model through using the pulse coding weight-mapping rule.In this work,we execute the inference of trained 5-layers convolution neural network on the memristor arrays and achieve an accuracy close to the inference in the case of high precision(64-bit).Compared with other algorithms-based off-chip learning,the algorithm proposed in the present study can easily implement the mapping process and less influence of the device variability.Our result provides an effective approach to implementing the ANN on the memristive hardware platform.展开更多
Using an in-house MMIC and an off-chip,high-quality varactor, a novel wide band VCO covered Ku band is introduced. In contrast to HMIC technology, this method reduces the complexity of microchip assembly. More importa...Using an in-house MMIC and an off-chip,high-quality varactor, a novel wide band VCO covered Ku band is introduced. In contrast to HMIC technology, this method reduces the complexity of microchip assembly. More importantly,it overcomes the constraint that the standard commercial GaAs pHEMT MMIC process is usually not compatible with highquality varactors for VCO,and it significantly improves the phase noise and frequency tuning linearity performances compared to either MMIC or HMIC implementation. It is a novel and high-quality method to develop microwave and millimeter wave VCO.展开更多
基于Nuvoton 0.5μm 5 V标准CMOS工艺,设计了一种高稳定性、高瞬态响应、无片外电容低压差线性稳压器(LDO)。电路中引入了过冲、欠冲电压改善模块,用来削减过/欠充电压,互不干扰。过冲电压改善电路将LDO输出电压与参考电压进行比较,过...基于Nuvoton 0.5μm 5 V标准CMOS工艺,设计了一种高稳定性、高瞬态响应、无片外电容低压差线性稳压器(LDO)。电路中引入了过冲、欠冲电压改善模块,用来削减过/欠充电压,互不干扰。过冲电压改善电路将LDO输出电压与参考电压进行比较,过冲状态下开启从LDO输出端到地的快速放电通路,欠冲电压改善电路通过电容耦合获得反映LDO输出电压瞬态变化的采样信号,经反向放大后加速功率管栅极电容放电,进而通过功率管对LDO输出电容充电。仿真结果表明,在TT工艺角下该低压差线性稳压器的空载相位裕度为64.57°,满载相位裕度为62.58°,过冲电压为40 m V,欠冲电压为97.6 m V,线性调整率为0.733‰;负载调整率19μV/m A;电源电压抑制比(PSRR)为-73 d B。展开更多
虽然批归一化算法能有效加速深度卷积网络模型的收敛速度,但其数据依赖性复杂,训练时会导致严重的“存储墙”瓶颈。故对使用批归一化算法的卷积神经网络,提出多层融合且重构批归一化层的训练方法,减少模型训练过程中的访存量。首先,通...虽然批归一化算法能有效加速深度卷积网络模型的收敛速度,但其数据依赖性复杂,训练时会导致严重的“存储墙”瓶颈。故对使用批归一化算法的卷积神经网络,提出多层融合且重构批归一化层的训练方法,减少模型训练过程中的访存量。首先,通过分析训练时批归一化层的数据依赖、访存特征及模型训练时的访存特征,分析访存瓶颈的关键因素;其次,使用“计算换访存”思想,提出融合“卷积层+批归一化层+激活层”结构的方法,并基于批归一化层的计算访存特征,将其重构为两个子层,分别与相邻层融合,进一步减少训练时对主存的读写,并构建了训练时的访存量模型与计算量模型。实验结果表明,使用NVIDIA TESLA V100 GPU训练ResNet-50、Inception V3及DenseNet模型时,同原始训练方法相比,其访存数据量分别降低了33%,22%及31%,V100的实际计算效率分别提升了20.5%,18.5%以及18.1%。这种优化方法利用了网络结构与模型训练时的访存特点,可与其他访存优化方法协同使用,进一步降低模型训练时的访存量。展开更多
设计了一款无需片外电容的LDO电路,根据负载不断变化的问题,设计了零极点跟踪补偿电路,使产生的零点有效补偿电路的极点,保证了LDO环路的稳定性。基于TSMC 0.18μm Flash工艺完成电路和版图的设计以及流片。电路仿真以及实测结果表明在...设计了一款无需片外电容的LDO电路,根据负载不断变化的问题,设计了零极点跟踪补偿电路,使产生的零点有效补偿电路的极点,保证了LDO环路的稳定性。基于TSMC 0.18μm Flash工艺完成电路和版图的设计以及流片。电路仿真以及实测结果表明在无片外电容的情况下,环路的相位裕度能够达到78.9°,达到高稳定的需求,最大负载电流能够达到100 m A,负载调整率为0.2 m V/m A。展开更多
基金The Key Science and Technology Project of Zhejiang Province(No.2007C21021)
文摘A CMOS （complementary metal-oxide-semiconductor transistor） low-dropout regulator （LDO） with 3. 3 V output voltage and 100 mA output current for system-on-chip applications to reduce board space and external pins is presented. By utilizing a dynamic slew-rate enhancement（SRE） circuit and nested Miller compensation （NMC） on the LDO structure, the proposed LDO provides high stability during line and load regulation without off-chip load capacitors. The overshot voltage is limited within 550 mV and the settling time is less than 50 μs when the load current decreases from 100 mA to 1 mA. By using a 30 nA reference current, the quiescent current is 3.3 μA. The proposed design is implemented by CSMC 0. 5 μm mixed-signal process. The experimental results agree with the simulation results.
基金the National Natural Science Foundation of China(Grant Nos.62076208,62076207,and U20A20227)the National Key Research and Development Program of China(Grant No.2018YFB1306600)。
文摘Memristive neural network has attracted tremendous attention since the memristor array can perform parallel multiplyaccumulate calculation(MAC)operations and memory-computation operations as compared with digital CMOS hardware systems.However,owing to the variability of the memristor,the implementation of high-precision neural network in memristive computation units is still difficult.Existing learning algorithms for memristive artificial neural network(ANN)is unable to achieve the performance comparable to high-precision by using CMOS-based system.Here,we propose an algorithm based on off-chip learning for memristive ANN in low precision.Training the ANN in the high-precision in digital CPUs and then quantifying the weight of the network to low precision,the quantified weights are mapped to the memristor arrays based on VTEAM model through using the pulse coding weight-mapping rule.In this work,we execute the inference of trained 5-layers convolution neural network on the memristor arrays and achieve an accuracy close to the inference in the case of high precision(64-bit).Compared with other algorithms-based off-chip learning,the algorithm proposed in the present study can easily implement the mapping process and less influence of the device variability.Our result provides an effective approach to implementing the ANN on the memristive hardware platform.
文摘Using an in-house MMIC and an off-chip,high-quality varactor, a novel wide band VCO covered Ku band is introduced. In contrast to HMIC technology, this method reduces the complexity of microchip assembly. More importantly,it overcomes the constraint that the standard commercial GaAs pHEMT MMIC process is usually not compatible with highquality varactors for VCO,and it significantly improves the phase noise and frequency tuning linearity performances compared to either MMIC or HMIC implementation. It is a novel and high-quality method to develop microwave and millimeter wave VCO.
文摘基于Nuvoton 0.5μm 5 V标准CMOS工艺,设计了一种高稳定性、高瞬态响应、无片外电容低压差线性稳压器(LDO)。电路中引入了过冲、欠冲电压改善模块,用来削减过/欠充电压,互不干扰。过冲电压改善电路将LDO输出电压与参考电压进行比较,过冲状态下开启从LDO输出端到地的快速放电通路,欠冲电压改善电路通过电容耦合获得反映LDO输出电压瞬态变化的采样信号,经反向放大后加速功率管栅极电容放电,进而通过功率管对LDO输出电容充电。仿真结果表明,在TT工艺角下该低压差线性稳压器的空载相位裕度为64.57°,满载相位裕度为62.58°,过冲电压为40 m V,欠冲电压为97.6 m V,线性调整率为0.733‰;负载调整率19μV/m A;电源电压抑制比(PSRR)为-73 d B。
文摘虽然批归一化算法能有效加速深度卷积网络模型的收敛速度,但其数据依赖性复杂,训练时会导致严重的“存储墙”瓶颈。故对使用批归一化算法的卷积神经网络,提出多层融合且重构批归一化层的训练方法,减少模型训练过程中的访存量。首先,通过分析训练时批归一化层的数据依赖、访存特征及模型训练时的访存特征,分析访存瓶颈的关键因素;其次,使用“计算换访存”思想,提出融合“卷积层+批归一化层+激活层”结构的方法,并基于批归一化层的计算访存特征,将其重构为两个子层,分别与相邻层融合,进一步减少训练时对主存的读写,并构建了训练时的访存量模型与计算量模型。实验结果表明,使用NVIDIA TESLA V100 GPU训练ResNet-50、Inception V3及DenseNet模型时,同原始训练方法相比,其访存数据量分别降低了33%,22%及31%,V100的实际计算效率分别提升了20.5%,18.5%以及18.1%。这种优化方法利用了网络结构与模型训练时的访存特点,可与其他访存优化方法协同使用,进一步降低模型训练时的访存量。
文摘设计了一款无需片外电容的LDO电路,根据负载不断变化的问题,设计了零极点跟踪补偿电路,使产生的零点有效补偿电路的极点,保证了LDO环路的稳定性。基于TSMC 0.18μm Flash工艺完成电路和版图的设计以及流片。电路仿真以及实测结果表明在无片外电容的情况下,环路的相位裕度能够达到78.9°,达到高稳定的需求,最大负载电流能够达到100 m A,负载调整率为0.2 m V/m A。
