Non-volatile memories(NVMs)provide lower latency and higher bandwidth than block devices.Besides,NVMs are byte-addressable and provide persistence that can be used as memory-level storage devices(non-volatile main mem...Non-volatile memories(NVMs)provide lower latency and higher bandwidth than block devices.Besides,NVMs are byte-addressable and provide persistence that can be used as memory-level storage devices(non-volatile main memory,NVMM).These features change storage hierarchy and allow CPU to access persistent data using load/store instructions.Thus,we can directly build a file system on NVMM.However,traditional file systems are designed based on slow block devices.They use a deep and complex software stack to optimize file system performance.This design results in software overhead being the dominant factor affecting NVMM file systems.Besides,scalability,crash consistency,data protection,and cross-media storage should be reconsidered in NVMM file systems.We survey existing work on optimizing NVMM file systems.First,we analyze the problems when directly using traditional file systems on NVMM,including heavy software overhead,limited scalability,inappropriate consistency guarantee techniques,etc.Second,we summarize the technique of 30 typical NVMM file systems and analyze their advantages and disadvantages.Finally,we provide a few suggestions for designing a high-performance NVMM file system based on real hardware Optane DC persistent memory module.Specifically,we suggest applying various techniques to reduce software overheads,improving the scalability of virtual file system(VFS),adopting highly-concurrent data structures(e.g.,lock and index),using memory protection keys(MPK)for data protection,and carefully designing data placement/migration for cross-media file system.展开更多
Non-Volatile Main Memories (NVMMs) have recently emerged as a promising technology for future memory systems. Generally, NVMMs have many desirable properties such as high density, byte-addressability, non-volatility, ...Non-Volatile Main Memories (NVMMs) have recently emerged as a promising technology for future memory systems. Generally, NVMMs have many desirable properties such as high density, byte-addressability, non-volatility, low cost, and energy efficiency, at the expense of high write latency, high write power consumption, and limited write endurance. NVMMs have become a competitive alternative of Dynamic Random Access Memory (DRAM), and will fundamentally change the landscape of memory systems. They bring many research opportunities as well as challenges on system architectural designs, memory management in operating systems (OSes), and programming models for hybrid memory systems. In this article, we revisit the landscape of emerging NVMM technologies, and then survey the state-of-the-art studies of NVMM technologies. We classify those studies with a taxonomy according to different dimensions such as memory architectures, data persistence, performance improvement, energy saving, and wear leveling. Second, to demonstrate the best practices in building NVMM systems, we introduce our recent work of hybrid memory system designs from the dimensions of architectures, systems, and applications. At last, we present our vision of future research directions of NVMMs and shed some light on design challenges and opportunities.展开更多
Image bitmaps,i.e.,data containing pixels and visual perception,have been widely used in emerging applica-tions for pixel operations while consuming lots of memory space and energy.Compared with legacy DRAM(dynamic ra...Image bitmaps,i.e.,data containing pixels and visual perception,have been widely used in emerging applica-tions for pixel operations while consuming lots of memory space and energy.Compared with legacy DRAM(dynamic ran-dom access memory),non-volatile memories(NVMs)are suitable for bitmap storage due to the salient features of high density and intrinsic durability.However,writing NVMs suffers from higher energy consumption and latency compared with read accesses.Existing precise or approximate compression schemes in NVM controllers show limited performance for bitmaps due to the irregular data patterns and variance in bitmaps.We observe the pixel-level similarity when writing bitmaps due to the analogous contents in adjacent pixels.By exploiting the pixel-level similarity,we propose SimCom,an approximate similarity-aware compression scheme in the NVM module controller,to efficiently compress data for each write access on-the-fly.The idea behind SimCom is to compress continuous similar words into the pairs of base words with runs.The storage costs for small runs are further mitigated by reusing the least significant bits of base words.SimCom adaptively selects an appropriate compression mode for various bitmap formats,thus achieving an efficient trade-off be-tween quality and memory performance.We implement SimCom on GEM5/zsim with NVMain and evaluate the perfor-mance with real-world image/video workloads.Our results demonstrate the efficacy and efficiency of our SimCom with an efficient quality-performance trade-off.展开更多
Single-poly,576bit non-volatile memory is designed and implemented in an SMIC 0.18μm standard CMOS process for the purpose of reducing the cost and power of passive RFID tag chips. The memory bit cell is designed wit...Single-poly,576bit non-volatile memory is designed and implemented in an SMIC 0.18μm standard CMOS process for the purpose of reducing the cost and power of passive RFID tag chips. The memory bit cell is designed with conventional single-poly pMOS transistors, based on the bi-directional Fowler-Nordheim tunneling effect, and the typical program/erase time is 10ms for every 16bits. A new ,single-ended sense amplifier is proposed to reduce the power dissipation in the current sensing scheme. The average current consumption of the whole memory chip is 0.8μA for the power supply voltage of 1.2V at a reading rate of 640kHz.展开更多
Organic ferroelectric memory devices based on field effect transistors that can be configured between two stable states of on and off have been widely researched as the next generation data storage media in recent yea...Organic ferroelectric memory devices based on field effect transistors that can be configured between two stable states of on and off have been widely researched as the next generation data storage media in recent years.This emerging type of memory devices can lead to a new instrument system as a potential alternative to previous non-volatile memory building blocks in future processing units because of their numerous merits such as cost-effective process,simple structure and freedom in substrate choices.This bi-stable non-volatile memory device of information storage has been investigated using several organic or inorganic semiconductors with organic ferroelectric polymer materials.Recent progresses in this ferroelectric memory field,hybrid system have attracted a lot of attention due to their excellent device performance in comparison with that of all organic systems.In this paper,a general review of this type of ferroelectric non-volatile memory is provided,which include the device structure,organic ferroelectric materials,electrical characteristics and working principles.We also present some snapshots of our previous study on hybrid ferroelectric memories including our recent work based on zinc oxide nanowire channels.展开更多
Magnetic tunnel junction(MTJ) based spin transfer torque magnetic random access memory(STT-MRAM) has been gaining tremendous momentum in high performance microcontroller(MCU) applications. As e Flash-replacement type ...Magnetic tunnel junction(MTJ) based spin transfer torque magnetic random access memory(STT-MRAM) has been gaining tremendous momentum in high performance microcontroller(MCU) applications. As e Flash-replacement type MRAM approaches mass production, there is an increasing demand for non-volatile RAM(nv RAM) technologies that offer fast write speed and high endurance. In this work, we demonstrate highly reliable 4 Mb nv RAM type MRAM suitable for industry and auto grade-1 applications. This nv RAM features retention over 10 years at 125 ℃, endurance of 1 × 10^(12)cycles with 20 ns write speed, making it ideal for applications requiring both high speed and broad temperature ranges. By employing innovative MTJ materials, process engineering, and a co-optimization of process and design, reliable read and write performance across the full temperature range between -40 to 125 ℃, and array yield that meets sub-1 ppm error rate was significantly improved from 0 to above 95%, a concrete step toward applications.展开更多
The non-volatile multi-level magnetic or resistance states switching is extremely promising for newgeneration high-density information storage.In this work,we propose a novel multiple-state magnetic memory based on th...The non-volatile multi-level magnetic or resistance states switching is extremely promising for newgeneration high-density information storage.In this work,we propose a novel multiple-state magnetic memory based on the magnetic deflagration in a single Laves-phase Tb_(0.95)Mn_(1.5)Co_(0.5)compound with non-volatile and multilevel magnetic states switching.In consideration of the negative magnetization,six different magnetic states are achieved by simply applying the magnetic field.The abinitio calculations and neutron diffraction measurements indicate that the studied compound is a cubic structure withferromagnetic ordering at low temperature and the evolution in magnetic states(i.e.magnetic deflagration)should arise from the Barkhausen effect.The almost unchanged magnetic state under corresponding range of magnetic field enables the magnetization to be in the same magnitude even after 50 cyclic hysteresis loops.Furthermore,the retention,repeatable switching,and non-volatile characters of multi-level magnetic state have been primely confirmed.All these suggest that the Tb_(0.95)Mn_(1.5)Co_(0.5)compound with multiple magnetic deflagrations could be applied to multiple-state magnetic memory and this work would pave the way to design a novel multi-level magnetic storage.展开更多
Non-volatile memory based on TiN nanocrystal （TiN-NC） charge storage nodes embedded in SiO2 has been fabricated and its electrical properties have been measured. It was found that the density and size distribution o...Non-volatile memory based on TiN nanocrystal （TiN-NC） charge storage nodes embedded in SiO2 has been fabricated and its electrical properties have been measured. It was found that the density and size distribution of TiN-NCs can be controlled by annealing temperature. The formation of well separated crystalline TiN nano-dots with an average size of 5 nm is confirmed by transmission electron microscopy and x-ray diffraction, x-ray photoelectron spectroscopy confirms the existence of a transition layer of TiNxOy/SiON oxide between TiN-NC and SiO2, which reduces the barrier height of tunnel oxide and thereby enhances programming/erasing speed. The memory device shows a memory window of 2.5V and an endurance cycle throughout 10^5. Its charging mechanism, which is interpreted from the analysis of programming speed （dVth/dt） and the gate leakage versus voltage characteristics （Ig vs Vg）, has been explained by direct tunnelling for tunnel oxide and Fowler Nordheim tunnelling for control oxide at programming voltages lower than 9V, and by Fowler-Nordheim tunnelling for both the oxides at programming voltages higher than 9V.展开更多
We design a nanostructure composing of two nanoscale graphene sheets parallelly immersed in water.Using molecular dynamics simulations,we demonstrate that the wet/dry state between the graphene sheets can be self-latc...We design a nanostructure composing of two nanoscale graphene sheets parallelly immersed in water.Using molecular dynamics simulations,we demonstrate that the wet/dry state between the graphene sheets can be self-latched;moreover,the wet→dry/dry→wet transition takes place when applying an external electric field perpendicular/parallel to the graphene sheets(E;/E;).This structure works like a flash memory device(a non-volatile memory):the stored information(wet and dry states)of the system can be kept spontaneously,and can also be rewritten by external electric fields.On the one hand,when the distance between the two nanosheets is close to a certain distance,the free energy barriers for the transitions dry→wet and wet→dry can be quite large.As a result,the wet and dry states are self-latched.On the other hand,an E;and an E;will respectively increase and decrease the free energy of the water located in-between the two nanosheets.Consequently,the wet→dry and dry→wet transitions are observed.Our results may be useful for designing novel information memory devices.展开更多
Low power consumption is a major issue in nowadays electronics systems. This trend is pushed by the development of data center related to cloud services and soon to the Internet of Things （IoT） deployment. Memories ...Low power consumption is a major issue in nowadays electronics systems. This trend is pushed by the development of data center related to cloud services and soon to the Internet of Things （IoT） deployment. Memories are one of the major contributors to power consumption. However, the development of emerging memory technologies paves the way to low-power design, through the partial replacement of the dynamic random access memory （DRAM） with the non-volatile stand-alone memory in servers or with the embedded or distributed emerging non-volatile memory in IoT objects. In the latter case, non-volatile flip-flops （NVFFs） seem a promising candidate to replace the retention latch. Indeed, IoT objects present long sleep time and NVFFs offer to save data in registers with zero power when the application is idle. This paper gives an overview of NVFF architecture flavors for various emerging memory technologies.展开更多
Exploiting new concepts for dense, fast, and nonvolatile random access memory with reduced energy consump- tion is a significant issue for information technology. Here we design an ＇electrically written and optically...Exploiting new concepts for dense, fast, and nonvolatile random access memory with reduced energy consump- tion is a significant issue for information technology. Here we design an ＇electrically written and optically read＇ information storage device employing BiFeO3/A u heterostruetures with strong absorption resonance. The electro- optic effect is the basis for the device design, which arises from the strong absorption resonance in BiFeO3/Au heterostructures and the electrically tunable significant birefringence of the BiFeO3 film. We first construct a sim- ulation calculation of the BiFeO3/Au structure spectrum and identify absorption resonance and electro-optical modulation characteristics. Following a micro scale partition, the surface reflected light intensity of different polarization units is calculated. The results depend on electric polarization states of the BiFeO3 film, thus BiFeO3/Au heterostructures can essentially be designed as a type of electrically written and optically read infor- mation storage device by utilizing the scanning near-field optical microscopy technology based on the conductive silicon cantilever tip with nanofabricated aperture. This work will shed light on information storage technology.展开更多
Recent studies have addressed that the cache be havior is important in the design of main memory index structures. Cache-conscious indices such as the CSB^＋-tree are shown to outperform conventional main memory indic...Recent studies have addressed that the cache be havior is important in the design of main memory index structures. Cache-conscious indices such as the CSB^＋-tree are shown to outperform conventional main memory indices such as the AVL-tree and the T-tree. This paper proposes a cacheconscious version of the T-tree, CST-tree, defined according to the cache-conscious definition. To separate the keys within a node into two parts, the CST-tree can gain higher cache hit ratio.展开更多
This paper presents an efficient recovery scheme suitable for real-time mainmemory database. In the recovery scheme, log records are stored in non-volatile RAM which is dividedinto four different partitions based on t...This paper presents an efficient recovery scheme suitable for real-time mainmemory database. In the recovery scheme, log records are stored in non-volatile RAM which is dividedinto four different partitions based on transaction types. Similarly, a main memory database isdivided into four partitions based data types. When the using ratio of log store area exceeds thethreshold value, checkpoint procedure is triggered. During executing checkpoint procedure, someuseless log records are deleted. During restart recovery after a crash, partition reloading policyis adopted to assure that critical data are reloaded and restored in advance, so that the databasesystem can be brought up before the entire database is reloaded into main memory. Therefore downtime is obvionsly reduced. Simulation experiments show our recovery scheme obviously improves thesystem performance, and does a favor to meet the dtadlints of real-time transactions.展开更多
The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power...The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.展开更多
BaTiO_(3)(BTO)ferroelectric films,which are renowned for their lead-free compositions,superior stability,and absence of a wake-up effect,are promising candidate materials in the field of non-volatile memories.However,...BaTiO_(3)(BTO)ferroelectric films,which are renowned for their lead-free compositions,superior stability,and absence of a wake-up effect,are promising candidate materials in the field of non-volatile memories.However,the prerequisites for high-temperature conditions in the fabrication of ferroelectric thin films impose constraints on the substrate choice,which has limited the advancement in non-volatile memories based on single-crystal flexible BTO films with robust ferroelectric properties.Herein,a technique has been developed for the fabrication of flexible devices using a pulsed laser deposition system.BTO ferroelectric films have then been deposited onto a flexible mica substrate,with SrTiO_(3)(STO)serving as a buffer layer.The obtained flexible BTO devices exhibited excellent ferroelectricity,with a maximum polarization(2Pmax)of up to 42.58μC/cm^(2) and a remnant polarization(2P_(r))of up to 21.39 μC/cm^(2).Furthermore,even after 1000 bending cycles,the bipolar switching endurance remained high at 1012 cycles.After 104 s,the flexible BTO device still maintained excellent polarization characteristics.These results make the flexible BTO ferroelectric thin film a potential candidate for the next generation of nonvolatile memories.展开更多
Facing the computing demands of Internet of things(IoT)and artificial intelligence(AI),the cost induced by moving the data between the central processing unit(CPU)and memory is the key problem and a chip featured with...Facing the computing demands of Internet of things(IoT)and artificial intelligence(AI),the cost induced by moving the data between the central processing unit(CPU)and memory is the key problem and a chip featured with flexible structural unit,ultra-low power consumption,and huge parallelism will be needed.In-memory computing,a non-von Neumann architecture fusing memory units and computing units,can eliminate the data transfer time and energy consumption while performing massive parallel computations.Prototype in-memory computing schemes modified from different memory technologies have shown orders of magnitude improvement in computing efficiency,making it be regarded as the ultimate computing paradigm.Here we review the state-of-the-art memory device technologies potential for in-memory computing,summarize their versatile applications in neural network,stochastic generation,and hybrid precision digital computing,with promising solutions for unprecedented computing tasks,and also discuss the challenges of stability and integration for general in-memory computing.展开更多
In the past decade,there has been tremendous progress in integrating chalcogenide phase-change materials(PCMs)on the silicon photonic platform for non-volatile memory to neuromorphic in-memory computing applications.I...In the past decade,there has been tremendous progress in integrating chalcogenide phase-change materials(PCMs)on the silicon photonic platform for non-volatile memory to neuromorphic in-memory computing applications.In particular,these non von Neumann computational elements and systems benefit from mass manufacturing of silicon photonic integrated circuits(PICs)on 8-inch wafers using a 130 nm complementary metal-oxide semiconductor line.Chip manufacturing based on deep-ultraviolet lithography and electron-beam lithography enables rapid prototyping of PICs,which can be integrated with high-quality PCMs based on the wafer-scale sputtering technique as a back-end-of-line process.In this article,we present an overview of recent advances in waveguide integrated PCM memory cells,functional devices,and neuromorphic systems,with an emphasis on fabrication and integration processes to attain state-of-the-art device performance.After a short overview of PCM based photonic devices,we discuss the materials properties of the functional layer as well as the progress on the light guiding layer,namely,the silicon and germanium waveguide platforms.Next,we discuss the cleanroom fabrication flow of waveguide devices integrated with thin films and nanowires,silicon waveguides and plasmonic microheaters for the electrothermal switching of PCMs and mixed-mode operation.Finally,the fabrication of photonic and photonic–electronic neuromorphic computing systems is reviewed.These systems consist of arrays of PCM memory elements for associative learning,matrix-vector multiplication,and pattern recognition.With large-scale integration,the neuromorphic photonic computing paradigm holds the promise to outperform digital electronic accelerators by taking the advantages of ultra-high bandwidth,high speed,and energy-efficient operation in running machine learning algorithms.展开更多
Wearable devices become popular because they can help people observe health condition.The battery life is the critical problem for wearable devices. The non-volatile memory(NVM) attracts attention in recent years beca...Wearable devices become popular because they can help people observe health condition.The battery life is the critical problem for wearable devices. The non-volatile memory(NVM) attracts attention in recent years because of its fast reading and writing speed, high density, persistence, and especially low idle power. With its low idle power consumption,NVM can be applied in wearable devices to prolong the battery lifetime such as smart bracelet. However, NVM has higher write power consumption than dynamic random access memory(DRAM). In this paper, we assume to use hybrid random access memory(RAM)and NVM architecture for the smart bracelet system.This paper presents a data management algorithm named bracelet power-aware data management(BPADM) based on the architecture. The BPADM can estimate the power consumption according to the memory access, such as sampling rate of data, and then determine the data should be stored in NVM or DRAM in order to satisfy low power. The experimental results show BPADM can reduce power consumption effectively for bracelet in normal and sleeping modes.展开更多
Non-volatile memory(NVM)provides a scalable and power-efficient solution to replace dynamic random access memory(DRAM)as main memory.However,because of the relatively high latency and low bandwidth of NVM,NVM is often...Non-volatile memory(NVM)provides a scalable and power-efficient solution to replace dynamic random access memory(DRAM)as main memory.However,because of the relatively high latency and low bandwidth of NVM,NVM is often paired with DRAM to build a heterogeneous memory system(HMS).As a result,data objects of the application must be carefully placed to NVM and DRAM for the best performance.In this paper,we introduce a lightweight runtime solution that automatically and transparently manages data placement on HMS without the requirement of hardware modifications and disruptive change to applications.Leveraging online profiling and performance models,the runtime solution characterizes memory access patterns associated with data objects,and minimizes unnecessary data movement.Our runtime solution effectively bridges the performance gap between NVM and DRAM.We demonstrate that using NVM to replace the majority of DRAM can be a feasible solution for future HPC systems with the assistance of a software-based data management.展开更多
With the full development of disk-resident databases(DRDB)in recent years,it is widely used in business and transactional applications.In long-term use,some problems of disk databases are gradually exposed.For applica...With the full development of disk-resident databases(DRDB)in recent years,it is widely used in business and transactional applications.In long-term use,some problems of disk databases are gradually exposed.For applications with high real-time requirements,the performance of using disk database is not satisfactory.In the context of the booming development of the Internet of things,domestic real-time databases have also gradually developed.Still,most of them only support the storage,processing,and analysis of data values with fewer data types,which can not fully meet the current industrial process control system data types,complex sources,fast update speed,and other needs.Facing the business needs of efficient data collection and storage of the Internet of things,this paper optimizes the transaction processing efficiency and data storage performance of the memory database,constructs a lightweight real-time memory database transaction processing and data storage model,realizes a lightweight real-time memory database transaction processing and data storage model,and improves the reliability and efficiency of the database.Through simulation,we proved that the cache hit rate of the cache replacement algorithm proposed in this paper is higher than the traditional LRU(Least Recently Used)algorithm.Using the cache replacement algorithm proposed in this paper can improve the performance of the system cache.展开更多
基金supported by the Major Research Plan of the National Natural Science Foundation of China under Grant No.92270202the Strategic Priority Research Program of the Chinese Academy of Sciences under Grant No.XDB44030200.
文摘Non-volatile memories(NVMs)provide lower latency and higher bandwidth than block devices.Besides,NVMs are byte-addressable and provide persistence that can be used as memory-level storage devices(non-volatile main memory,NVMM).These features change storage hierarchy and allow CPU to access persistent data using load/store instructions.Thus,we can directly build a file system on NVMM.However,traditional file systems are designed based on slow block devices.They use a deep and complex software stack to optimize file system performance.This design results in software overhead being the dominant factor affecting NVMM file systems.Besides,scalability,crash consistency,data protection,and cross-media storage should be reconsidered in NVMM file systems.We survey existing work on optimizing NVMM file systems.First,we analyze the problems when directly using traditional file systems on NVMM,including heavy software overhead,limited scalability,inappropriate consistency guarantee techniques,etc.Second,we summarize the technique of 30 typical NVMM file systems and analyze their advantages and disadvantages.Finally,we provide a few suggestions for designing a high-performance NVMM file system based on real hardware Optane DC persistent memory module.Specifically,we suggest applying various techniques to reduce software overheads,improving the scalability of virtual file system(VFS),adopting highly-concurrent data structures(e.g.,lock and index),using memory protection keys(MPK)for data protection,and carefully designing data placement/migration for cross-media file system.
基金Supported jointly by the National Natural Science Foundation of China under Grants Nos. 61672251, 61732010, 61825202, and 61929103.
文摘Non-Volatile Main Memories (NVMMs) have recently emerged as a promising technology for future memory systems. Generally, NVMMs have many desirable properties such as high density, byte-addressability, non-volatility, low cost, and energy efficiency, at the expense of high write latency, high write power consumption, and limited write endurance. NVMMs have become a competitive alternative of Dynamic Random Access Memory (DRAM), and will fundamentally change the landscape of memory systems. They bring many research opportunities as well as challenges on system architectural designs, memory management in operating systems (OSes), and programming models for hybrid memory systems. In this article, we revisit the landscape of emerging NVMM technologies, and then survey the state-of-the-art studies of NVMM technologies. We classify those studies with a taxonomy according to different dimensions such as memory architectures, data persistence, performance improvement, energy saving, and wear leveling. Second, to demonstrate the best practices in building NVMM systems, we introduce our recent work of hybrid memory system designs from the dimensions of architectures, systems, and applications. At last, we present our vision of future research directions of NVMMs and shed some light on design challenges and opportunities.
基金This work was supported in part by the National Natural Science Foundation of China under Grant Nos.62125202 and U22B2022.
文摘Image bitmaps,i.e.,data containing pixels and visual perception,have been widely used in emerging applica-tions for pixel operations while consuming lots of memory space and energy.Compared with legacy DRAM(dynamic ran-dom access memory),non-volatile memories(NVMs)are suitable for bitmap storage due to the salient features of high density and intrinsic durability.However,writing NVMs suffers from higher energy consumption and latency compared with read accesses.Existing precise or approximate compression schemes in NVM controllers show limited performance for bitmaps due to the irregular data patterns and variance in bitmaps.We observe the pixel-level similarity when writing bitmaps due to the analogous contents in adjacent pixels.By exploiting the pixel-level similarity,we propose SimCom,an approximate similarity-aware compression scheme in the NVM module controller,to efficiently compress data for each write access on-the-fly.The idea behind SimCom is to compress continuous similar words into the pairs of base words with runs.The storage costs for small runs are further mitigated by reusing the least significant bits of base words.SimCom adaptively selects an appropriate compression mode for various bitmap formats,thus achieving an efficient trade-off be-tween quality and memory performance.We implement SimCom on GEM5/zsim with NVMain and evaluate the perfor-mance with real-world image/video workloads.Our results demonstrate the efficacy and efficiency of our SimCom with an efficient quality-performance trade-off.
文摘Single-poly,576bit non-volatile memory is designed and implemented in an SMIC 0.18μm standard CMOS process for the purpose of reducing the cost and power of passive RFID tag chips. The memory bit cell is designed with conventional single-poly pMOS transistors, based on the bi-directional Fowler-Nordheim tunneling effect, and the typical program/erase time is 10ms for every 16bits. A new ,single-ended sense amplifier is proposed to reduce the power dissipation in the current sensing scheme. The average current consumption of the whole memory chip is 0.8μA for the power supply voltage of 1.2V at a reading rate of 640kHz.
文摘Organic ferroelectric memory devices based on field effect transistors that can be configured between two stable states of on and off have been widely researched as the next generation data storage media in recent years.This emerging type of memory devices can lead to a new instrument system as a potential alternative to previous non-volatile memory building blocks in future processing units because of their numerous merits such as cost-effective process,simple structure and freedom in substrate choices.This bi-stable non-volatile memory device of information storage has been investigated using several organic or inorganic semiconductors with organic ferroelectric polymer materials.Recent progresses in this ferroelectric memory field,hybrid system have attracted a lot of attention due to their excellent device performance in comparison with that of all organic systems.In this paper,a general review of this type of ferroelectric non-volatile memory is provided,which include the device structure,organic ferroelectric materials,electrical characteristics and working principles.We also present some snapshots of our previous study on hybrid ferroelectric memories including our recent work based on zinc oxide nanowire channels.
基金supported by National Science and Technology Major Project (2020AAA0109003)the support from Hangzhou Innovation Team Program (TD2022018)。
文摘Magnetic tunnel junction(MTJ) based spin transfer torque magnetic random access memory(STT-MRAM) has been gaining tremendous momentum in high performance microcontroller(MCU) applications. As e Flash-replacement type MRAM approaches mass production, there is an increasing demand for non-volatile RAM(nv RAM) technologies that offer fast write speed and high endurance. In this work, we demonstrate highly reliable 4 Mb nv RAM type MRAM suitable for industry and auto grade-1 applications. This nv RAM features retention over 10 years at 125 ℃, endurance of 1 × 10^(12)cycles with 20 ns write speed, making it ideal for applications requiring both high speed and broad temperature ranges. By employing innovative MTJ materials, process engineering, and a co-optimization of process and design, reliable read and write performance across the full temperature range between -40 to 125 ℃, and array yield that meets sub-1 ppm error rate was significantly improved from 0 to above 95%, a concrete step toward applications.
基金financially supported by the National Natural Science Foundation of China(No.52061014)the Natural Science Foundation of Henan Province(No.242300420352)+4 种基金the Key research and development program of Henan province(No.231111222200)the Key Scientific Research Projects of Higher Education Institutions in Henan Province(No.25CY025)the Leading Talents Program of Jiangxi Provincial Major Discipline Academic and Technical Leaders Training Program(No.20204BCJ22004)the Open Project awarded by Fujian Provincial Key Laboratory of Quantum Manipulation and New Energy Materials(No.QMNEM2002)Jiangxi Provincial Key Laboratory of Magnetic Metallic Materials and Devices(No.2024SSY05061)
文摘The non-volatile multi-level magnetic or resistance states switching is extremely promising for newgeneration high-density information storage.In this work,we propose a novel multiple-state magnetic memory based on the magnetic deflagration in a single Laves-phase Tb_(0.95)Mn_(1.5)Co_(0.5)compound with non-volatile and multilevel magnetic states switching.In consideration of the negative magnetization,six different magnetic states are achieved by simply applying the magnetic field.The abinitio calculations and neutron diffraction measurements indicate that the studied compound is a cubic structure withferromagnetic ordering at low temperature and the evolution in magnetic states(i.e.magnetic deflagration)should arise from the Barkhausen effect.The almost unchanged magnetic state under corresponding range of magnetic field enables the magnetization to be in the same magnitude even after 50 cyclic hysteresis loops.Furthermore,the retention,repeatable switching,and non-volatile characters of multi-level magnetic state have been primely confirmed.All these suggest that the Tb_(0.95)Mn_(1.5)Co_(0.5)compound with multiple magnetic deflagrations could be applied to multiple-state magnetic memory and this work would pave the way to design a novel multi-level magnetic storage.
文摘Non-volatile memory based on TiN nanocrystal （TiN-NC） charge storage nodes embedded in SiO2 has been fabricated and its electrical properties have been measured. It was found that the density and size distribution of TiN-NCs can be controlled by annealing temperature. The formation of well separated crystalline TiN nano-dots with an average size of 5 nm is confirmed by transmission electron microscopy and x-ray diffraction, x-ray photoelectron spectroscopy confirms the existence of a transition layer of TiNxOy/SiON oxide between TiN-NC and SiO2, which reduces the barrier height of tunnel oxide and thereby enhances programming/erasing speed. The memory device shows a memory window of 2.5V and an endurance cycle throughout 10^5. Its charging mechanism, which is interpreted from the analysis of programming speed （dVth/dt） and the gate leakage versus voltage characteristics （Ig vs Vg）, has been explained by direct tunnelling for tunnel oxide and Fowler Nordheim tunnelling for control oxide at programming voltages lower than 9V, and by Fowler-Nordheim tunnelling for both the oxides at programming voltages higher than 9V.
基金supported by the National Natural Science Foundation of China(Grant No.11704328)。
文摘We design a nanostructure composing of two nanoscale graphene sheets parallelly immersed in water.Using molecular dynamics simulations,we demonstrate that the wet/dry state between the graphene sheets can be self-latched;moreover,the wet→dry/dry→wet transition takes place when applying an external electric field perpendicular/parallel to the graphene sheets(E;/E;).This structure works like a flash memory device(a non-volatile memory):the stored information(wet and dry states)of the system can be kept spontaneously,and can also be rewritten by external electric fields.On the one hand,when the distance between the two nanosheets is close to a certain distance,the free energy barriers for the transitions dry→wet and wet→dry can be quite large.As a result,the wet and dry states are self-latched.On the other hand,an E;and an E;will respectively increase and decrease the free energy of the water located in-between the two nanosheets.Consequently,the wet→dry and dry→wet transitions are observed.Our results may be useful for designing novel information memory devices.
基金supported by the ANR project DIPMEM under Grant No.ANR-12-NANO-0010-04
文摘Low power consumption is a major issue in nowadays electronics systems. This trend is pushed by the development of data center related to cloud services and soon to the Internet of Things （IoT） deployment. Memories are one of the major contributors to power consumption. However, the development of emerging memory technologies paves the way to low-power design, through the partial replacement of the dynamic random access memory （DRAM） with the non-volatile stand-alone memory in servers or with the embedded or distributed emerging non-volatile memory in IoT objects. In the latter case, non-volatile flip-flops （NVFFs） seem a promising candidate to replace the retention latch. Indeed, IoT objects present long sleep time and NVFFs offer to save data in registers with zero power when the application is idle. This paper gives an overview of NVFF architecture flavors for various emerging memory technologies.
基金Supported by the National Natural Science Foundation of China under Grant No 11304384the Research Project of National University of Defense Technology under Grant No JC13-07-02
文摘Exploiting new concepts for dense, fast, and nonvolatile random access memory with reduced energy consump- tion is a significant issue for information technology. Here we design an ＇electrically written and optically read＇ information storage device employing BiFeO3/A u heterostruetures with strong absorption resonance. The electro- optic effect is the basis for the device design, which arises from the strong absorption resonance in BiFeO3/Au heterostructures and the electrically tunable significant birefringence of the BiFeO3 film. We first construct a sim- ulation calculation of the BiFeO3/Au structure spectrum and identify absorption resonance and electro-optical modulation characteristics. Following a micro scale partition, the surface reflected light intensity of different polarization units is calculated. The results depend on electric polarization states of the BiFeO3 film, thus BiFeO3/Au heterostructures can essentially be designed as a type of electrically written and optically read infor- mation storage device by utilizing the scanning near-field optical microscopy technology based on the conductive silicon cantilever tip with nanofabricated aperture. This work will shed light on information storage technology.
基金Supported bythe National High Technology of 863Project (2002AA1Z2308 ,2002AA118030)
文摘Recent studies have addressed that the cache be havior is important in the design of main memory index structures. Cache-conscious indices such as the CSB^＋-tree are shown to outperform conventional main memory indices such as the AVL-tree and the T-tree. This paper proposes a cacheconscious version of the T-tree, CST-tree, defined according to the cache-conscious definition. To separate the keys within a node into two parts, the CST-tree can gain higher cache hit ratio.
文摘This paper presents an efficient recovery scheme suitable for real-time mainmemory database. In the recovery scheme, log records are stored in non-volatile RAM which is dividedinto four different partitions based on transaction types. Similarly, a main memory database isdivided into four partitions based data types. When the using ratio of log store area exceeds thethreshold value, checkpoint procedure is triggered. During executing checkpoint procedure, someuseless log records are deleted. During restart recovery after a crash, partition reloading policyis adopted to assure that critical data are reloaded and restored in advance, so that the databasesystem can be brought up before the entire database is reloaded into main memory. Therefore downtime is obvionsly reduced. Simulation experiments show our recovery scheme obviously improves thesystem performance, and does a favor to meet the dtadlints of real-time transactions.
基金supported in part by the National Natural Science Foundation of China(No.61306027)
文摘The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.
基金support by Guangxi Natural Science Foundation(NO.2023GXNSFBA026216)National Natural Science Foundation of China(NO.62361022,52061009,61964003,52262022,62174041).
文摘BaTiO_(3)(BTO)ferroelectric films,which are renowned for their lead-free compositions,superior stability,and absence of a wake-up effect,are promising candidate materials in the field of non-volatile memories.However,the prerequisites for high-temperature conditions in the fabrication of ferroelectric thin films impose constraints on the substrate choice,which has limited the advancement in non-volatile memories based on single-crystal flexible BTO films with robust ferroelectric properties.Herein,a technique has been developed for the fabrication of flexible devices using a pulsed laser deposition system.BTO ferroelectric films have then been deposited onto a flexible mica substrate,with SrTiO_(3)(STO)serving as a buffer layer.The obtained flexible BTO devices exhibited excellent ferroelectricity,with a maximum polarization(2Pmax)of up to 42.58μC/cm^(2) and a remnant polarization(2P_(r))of up to 21.39 μC/cm^(2).Furthermore,even after 1000 bending cycles,the bipolar switching endurance remained high at 1012 cycles.After 104 s,the flexible BTO device still maintained excellent polarization characteristics.These results make the flexible BTO ferroelectric thin film a potential candidate for the next generation of nonvolatile memories.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61925402 and 61851402)Science and Technology Commission of Shanghai Municipality,China(Grant No.19JC1416600)+1 种基金the National Key Research and Development Program of China(Grant No.2017YFB0405600)Shanghai Education Development Foundation and Shanghai Municipal Education Commission Shuguang Program,China(Grant No.18SG01).
文摘Facing the computing demands of Internet of things(IoT)and artificial intelligence(AI),the cost induced by moving the data between the central processing unit(CPU)and memory is the key problem and a chip featured with flexible structural unit,ultra-low power consumption,and huge parallelism will be needed.In-memory computing,a non-von Neumann architecture fusing memory units and computing units,can eliminate the data transfer time and energy consumption while performing massive parallel computations.Prototype in-memory computing schemes modified from different memory technologies have shown orders of magnitude improvement in computing efficiency,making it be regarded as the ultimate computing paradigm.Here we review the state-of-the-art memory device technologies potential for in-memory computing,summarize their versatile applications in neural network,stochastic generation,and hybrid precision digital computing,with promising solutions for unprecedented computing tasks,and also discuss the challenges of stability and integration for general in-memory computing.
基金the support of the National Natural Science Foundation of China(Grant No.62204201)。
文摘In the past decade,there has been tremendous progress in integrating chalcogenide phase-change materials(PCMs)on the silicon photonic platform for non-volatile memory to neuromorphic in-memory computing applications.In particular,these non von Neumann computational elements and systems benefit from mass manufacturing of silicon photonic integrated circuits(PICs)on 8-inch wafers using a 130 nm complementary metal-oxide semiconductor line.Chip manufacturing based on deep-ultraviolet lithography and electron-beam lithography enables rapid prototyping of PICs,which can be integrated with high-quality PCMs based on the wafer-scale sputtering technique as a back-end-of-line process.In this article,we present an overview of recent advances in waveguide integrated PCM memory cells,functional devices,and neuromorphic systems,with an emphasis on fabrication and integration processes to attain state-of-the-art device performance.After a short overview of PCM based photonic devices,we discuss the materials properties of the functional layer as well as the progress on the light guiding layer,namely,the silicon and germanium waveguide platforms.Next,we discuss the cleanroom fabrication flow of waveguide devices integrated with thin films and nanowires,silicon waveguides and plasmonic microheaters for the electrothermal switching of PCMs and mixed-mode operation.Finally,the fabrication of photonic and photonic–electronic neuromorphic computing systems is reviewed.These systems consist of arrays of PCM memory elements for associative learning,matrix-vector multiplication,and pattern recognition.With large-scale integration,the neuromorphic photonic computing paradigm holds the promise to outperform digital electronic accelerators by taking the advantages of ultra-high bandwidth,high speed,and energy-efficient operation in running machine learning algorithms.
基金supported by the Research Fund of National Key Laboratory of Computer Architecture under Grant No.CARCH201501the Open Project Program of the State Key Laboratory of Mathematical Engineering and Advanced Computing under Grant No.2016A09
文摘Wearable devices become popular because they can help people observe health condition.The battery life is the critical problem for wearable devices. The non-volatile memory(NVM) attracts attention in recent years because of its fast reading and writing speed, high density, persistence, and especially low idle power. With its low idle power consumption,NVM can be applied in wearable devices to prolong the battery lifetime such as smart bracelet. However, NVM has higher write power consumption than dynamic random access memory(DRAM). In this paper, we assume to use hybrid random access memory(RAM)and NVM architecture for the smart bracelet system.This paper presents a data management algorithm named bracelet power-aware data management(BPADM) based on the architecture. The BPADM can estimate the power consumption according to the memory access, such as sampling rate of data, and then determine the data should be stored in NVM or DRAM in order to satisfy low power. The experimental results show BPADM can reduce power consumption effectively for bracelet in normal and sleeping modes.
基金Supported by the U.S. National Science Foundation under Grant Nos. CNS-1617967, CCF-1553645, and CCF1718194。
文摘Non-volatile memory(NVM)provides a scalable and power-efficient solution to replace dynamic random access memory(DRAM)as main memory.However,because of the relatively high latency and low bandwidth of NVM,NVM is often paired with DRAM to build a heterogeneous memory system(HMS).As a result,data objects of the application must be carefully placed to NVM and DRAM for the best performance.In this paper,we introduce a lightweight runtime solution that automatically and transparently manages data placement on HMS without the requirement of hardware modifications and disruptive change to applications.Leveraging online profiling and performance models,the runtime solution characterizes memory access patterns associated with data objects,and minimizes unnecessary data movement.Our runtime solution effectively bridges the performance gap between NVM and DRAM.We demonstrate that using NVM to replace the majority of DRAM can be a feasible solution for future HPC systems with the assistance of a software-based data management.
基金supported by the National Key R&D Program of China“Key technologies for coordination and interoperation of power distribution service resource”[2021YFB1302400]“Research on Digitization and Intelligent Application of Low-Voltage Power Distribution Equipment”[SGSDDK00PDJS2000375].
文摘With the full development of disk-resident databases(DRDB)in recent years,it is widely used in business and transactional applications.In long-term use,some problems of disk databases are gradually exposed.For applications with high real-time requirements,the performance of using disk database is not satisfactory.In the context of the booming development of the Internet of things,domestic real-time databases have also gradually developed.Still,most of them only support the storage,processing,and analysis of data values with fewer data types,which can not fully meet the current industrial process control system data types,complex sources,fast update speed,and other needs.Facing the business needs of efficient data collection and storage of the Internet of things,this paper optimizes the transaction processing efficiency and data storage performance of the memory database,constructs a lightweight real-time memory database transaction processing and data storage model,realizes a lightweight real-time memory database transaction processing and data storage model,and improves the reliability and efficiency of the database.Through simulation,we proved that the cache hit rate of the cache replacement algorithm proposed in this paper is higher than the traditional LRU(Least Recently Used)algorithm.Using the cache replacement algorithm proposed in this paper can improve the performance of the system cache.
