In this paper, we present a graphics processing unit(GPU)-based implementation of a weighted bit-reliability based(w BRB) decoder for non-binary LDPC(NB-LDPC) codes. To achieve coalesced memory accesses, an efficient ...In this paper, we present a graphics processing unit(GPU)-based implementation of a weighted bit-reliability based(w BRB) decoder for non-binary LDPC(NB-LDPC) codes. To achieve coalesced memory accesses, an efficient data structure for the w BRB algorithm is proposed. Based on the Single-Instruction Multiple-Threads(SIMT) programming model, a novel mapping strategy with high intra-frame parallelism is presented to improve the latency and throughput performance. Moreover, by using Single-Instruction Multiple-Data(SIMD) intrinsics, four 8-bit message elements are packed into a 32-bit unit and simultaneously processed. Experimental results show that the proposed w BRB decoder provides good tradeoff between error performance and throughput for the codes with relatively large column degrees or high rates.展开更多
A modified Benes network is proposed to be used as an optimal shuffle network in worldwide interoperability for microwave access （WiMAX） low density parity check （LDPC） decoders, When the size of the input is not ...A modified Benes network is proposed to be used as an optimal shuffle network in worldwide interoperability for microwave access （WiMAX） low density parity check （LDPC） decoders, When the size of the input is not a power of two, the modified Benes network can achieve the most optimal performance. This modified Benes network is non-blocking and can perform any sorts of permutations, so it can support 19 modes specified in the WiMAX system. Furthermore, an efficient algorithm to generate the control signals for all the 2 × 2 switches in this network is derived, which can reduce the hardware complexity and overall latency of the modified Benes network. Synthesis results show that the proposed control signal generator can save 25.4% chip area and the overall network latency can be reduced by 36. 2%.展开更多
In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC)decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC)...In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC)decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC)LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU)and the variable node unit(VNU)based on min-sum(MS)algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT)is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction.展开更多
Decoding by alternating direction method of multipliers(ADMM) is a promising linear programming decoder for low-density parity-check(LDPC) codes. In this paper, we propose a two-step scheme to lower the error floor of...Decoding by alternating direction method of multipliers(ADMM) is a promising linear programming decoder for low-density parity-check(LDPC) codes. In this paper, we propose a two-step scheme to lower the error floor of LDPC codes with ADMM penalized decoder.For the undetected errors that cannot be avoided at the decoder side, we modify the code structure slightly to eliminate low-weight code words. For the detected errors induced by small error-prone structures, we propose a post-processing method for the ADMM penalized decoder. Simulation results show that the error floor can be reduced significantly over three illustrated LDPC codes by the proposed two-step scheme.展开更多
Space laser communication(SLC)is an emerging technology to support high-throughput data transmissions in space networks.In this paper,to guarantee the reliability of high-speed SLC links,we aim at practical implementa...Space laser communication(SLC)is an emerging technology to support high-throughput data transmissions in space networks.In this paper,to guarantee the reliability of high-speed SLC links,we aim at practical implementation of low-density paritycheck(LDPC)decoding under resource-restricted space platforms.Particularly,due to the supply restriction and cost issues of high-speed on-board devices such as analog-to-digital converters(ADCs),the input of LDPC decoding will be usually constrained by hard-decision channel output.To tackle this challenge,density-evolution-based theoretical analysis is firstly performed to identify the cause of performance degradation in the conventional binaryinitialized iterative decoding(BIID)algorithm.Then,a computation-efficient decoding algorithm named multiary-initialized iterative decoding with early termination(MIID-ET)is proposed,which improves the error-correcting performance and computation efficiency by using a reliability-based initialization method and a threshold-based decoding termination rule.Finally,numerical simulations are conducted on example codes of rates 7/8 and 1/2 to evaluate the performance of different LDPC decoding algorithms,where the proposed MIID-ET outperforms the BIID with a coding gain of 0.38 dB and variable node calculation saving of 37%.With this advantage,the proposed MIID-ET can notably reduce LDPC decoder’s hardware implementation complexity under the same bit error rate performance,which successfully doubles the total throughput to 10 Gbps on a single-chip FPGA.展开更多
Considering that the hardware implementation of the normalized minimum sum(NMS)decoding algorithm for low-density parity-check(LDPC)code is difficult due to the uncertainty of scale factor,an NMS decoding algorithm wi...Considering that the hardware implementation of the normalized minimum sum(NMS)decoding algorithm for low-density parity-check(LDPC)code is difficult due to the uncertainty of scale factor,an NMS decoding algorithm with variable scale factor is proposed for the near-earth space LDPC codes(8177,7154)in the consultative committee for space data systems(CCSDS)standard.The shift characteristics of field programmable gate array(FPGA)is used to optimize the quantization data of check nodes,and finally the function of LDPC decoder is realized.The simulation and experimental results show that the designed FPGA-based LDPC decoder adopts the scaling factor in the NMS decoding algorithm to improve the decoding performance,simplify the hardware structure,accelerate the convergence speed and improve the error correction ability.展开更多
The conventional methodology for designing QC-LDPC decoders is applied for fixed configurations used in wireless communication standards, and the supported largest expansion factor Z (the parallelism of the layered de...The conventional methodology for designing QC-LDPC decoders is applied for fixed configurations used in wireless communication standards, and the supported largest expansion factor Z (the parallelism of the layered decoding) is a fixed number. In this paper, we study the circular-shifting network for decoding LDPC codes with arbitrary Z factor, especially for decoding large Z (Z P) codes, where P is the decoder parallelism. By buffering the P-length slices from the memory, and assembling the shifted slices in a fixed routine, the P-parallelism shift network can process Z-parallelism circular-shifting tasks. The implementation results show that the proposed network for arbitrary sized data shifting consumes only one times of additional resource cost compared to the traditional solution for only maximum P sized data shifting, and achieves significant saving on area and routing complexity.展开更多
A novel low-complexity weighted symbol-flipping algorithm with flipping patterns to decode nonbinary low-density parity-check codes is proposed. The proposed decoding procedure updates the hard-decision received symbo...A novel low-complexity weighted symbol-flipping algorithm with flipping patterns to decode nonbinary low-density parity-check codes is proposed. The proposed decoding procedure updates the hard-decision received symbol vector iteratively in search of a valid codeword in the symbol vector space. Only one symbol is flipped in each iteration, and symbol flipping function, which is employed as the symbol flipping metric, combines the number of failed checks and the reliabilities of the received bits and calculated symbols. A scheme to avoid infinite loops and select one symbol to flip in high order Galois field search is also proposed. The design of flipping pattern＇s order and depth, which is dependent of the computational requirement and error performance, is also proposed and exemplified. Simulation results show that the algorithm achieves an appealing tradeoff between performance and computational requirement over relatively low Galois field for short to medium code length.展开更多
Abstract： The layered decoding algorithm has been widely used in the implementation of Low Density Parity Check （LDPC） decoders, due to its high convergence speed. However, the pipeline operation of the layered dec...Abstract： The layered decoding algorithm has been widely used in the implementation of Low Density Parity Check （LDPC） decoders, due to its high convergence speed. However, the pipeline operation of the layered decoder may introduce memory access conflicts, which heavily deteriorates the decoder throughput. To essentially deal with the issue of memory access conflicts,展开更多
This paper presents a simple yet effective decoding for general quasi-cyclic low-density parity-check （QC-LDPC） codes, which not only achieves high hardware utility efficiency （HUE）, but also brings about great me...This paper presents a simple yet effective decoding for general quasi-cyclic low-density parity-check （QC-LDPC） codes, which not only achieves high hardware utility efficiency （HUE）, but also brings about great memory block reduction without any performance degradation. The main idea is to split the check matrix into several row blocks, then to perform the improved mes- sage passing computations sequentially block by block. As the decoding algorithm improves, the sequential tie between the two-phase computations is broken, so that the two-phase computations can be overlapped which bring in high HUE. Two over- lapping schemes are also presented, each of which suits a different situation. In addition, an efficient memory arrangement scheme is proposed to reduce the great memory block requirement of the LDPC decoder. As an example, for the 0.4 rate LDPC code selected from Chinese Digital TV Terrestrial Broadcasting （DTTB）, our decoding saves over 80% memory blocks com- pared with the conventional decoding, and the decoder achieves 0.97 HUE. Finally, the 0.4 rate LDPC decoder is implemented on an FPGA device EP2S30 （speed grade -5）. Using 8 row processing units, the decoder can achieve a maximum net throughput of 28.5 Mbps at 20 iterations.展开更多
Binary Polar Codes (BPCs) have advantages of high-efficiency and capacity-achieving but suffer from large latency due to the Successive-Cancellation List (SCL) decoding. Non-Binary Polar Codes (NBPCs) have been invest...Binary Polar Codes (BPCs) have advantages of high-efficiency and capacity-achieving but suffer from large latency due to the Successive-Cancellation List (SCL) decoding. Non-Binary Polar Codes (NBPCs) have been investigated to obtain the performance gains and reduce latency under the implementation of parallel architectures for multi-bit decoding. However, most of the existing works only focus on the Reed-Solomon matrix-based NBPCs and the probability domain-based non-binary polar decoding, which lack flexible structure and have a large computation amount in the decoding process, while little attention has been paid to general non-binary kernel-based NBPCs and Log-Likelihood Ratio (LLR) based decoding methods. In this paper, we consider a scheme of NBPCs with a general structure over GF(2m). Specifically, we pursue a detailed Monte-Carlo simulation implementation to determine the construction for proposed NBPCs. For non-binary polar decoding, an SCL decoding based on LLRs is proposed for NBPCs, which can be implemented with non-binary kernels of arbitrary size. Moreover, we propose a Perfect Polarization-Based SCL (PPB-SCL) algorithm based on LLRs to reduce decoding complexity by deriving a new update function of path metric for NBPCs and eliminating the path splitting process at perfect polarized (i.e., highly reliable) positions. Simulation results show that the bit error rate of the proposed NBPCs significantly outperforms that of BPCs. In addition, the proposed PPB-SCL decoding obtains about a 40% complexity reduction of SCL decoding for NBPCs.展开更多
Non-uniform quantization for messages in Low-Density Parity-Check(LDPC)decoding canreduce implementation complexity and mitigate performance loss.But the distribution of messagesvaries in the iterative decoding.This l...Non-uniform quantization for messages in Low-Density Parity-Check(LDPC)decoding canreduce implementation complexity and mitigate performance loss.But the distribution of messagesvaries in the iterative decoding.This letter proposes a variable non-uniform quantized Belief Propaga-tion(BP)algorithm.The BP decoding is analyzed by density evolution with Gaussian approximation.Since the probability density of messages can be well approximated by Gaussian distribution,by theunbiased estimation of variance,the distribution of messages can be tracked during the iteration.Thusthe non-uniform quantization scheme can be optimized to minimize the distortion.Simulation resultsshow that the variable non-uniform quantization scheme can achieve better error rate performance andfaster decoding convergence than the conventional non-uniform quantization and uniform quantizationschemes.展开更多
An iterative detection/decoding algorithm of correlated sources for the LDPC-based relay systems is presented. The signal from the source-destination(S-D) link is formulated as a highly correlated counterpart from the...An iterative detection/decoding algorithm of correlated sources for the LDPC-based relay systems is presented. The signal from the source-destination(S-D) link is formulated as a highly correlated counterpart from the relay-destination(R-D) link. A special XOR vector is defined using the correlated hard decision information blocks from two decoders and the extrinsic information exchanged between the two decoders is derived by the log-likelihood ratio(LLR) associated with the XOR vector. Such the decoding scheme is different from the traditional turbo-like detection/decoding algorithm, where the extrinsic information is computed by the side information and the soft decoder outputs. Simulations show that the presented algorithm has a slightly better performance than the traditional turbo-like algorithm(Taking the(255,175) EG-LDPC code as an example, it achieves about 0.1 dB performance gains aroundBLER=10^(-4)). Furthermore, the presented algorithm requires fewer computing operations per iteration and has faster convergence rate. For example, the average iteration of the presented algorithm is 33 at SNR=1.8 dB, which is about twice faster than that of the turbo-like algorithm, when decoding the(961,721) QC-LDPC code. Therefore, the presented decoding algorithm of correlated sources provides an alternative decoding solution for the LDPC-based relay systems.展开更多
<div style="text-align:justify;"> Low-density parity-check code (LDPC) not only has good performance approaching the Shannon limit, but also has low decoding complexity and flexible structure. It is a ...<div style="text-align:justify;"> Low-density parity-check code (LDPC) not only has good performance approaching the Shannon limit, but also has low decoding complexity and flexible structure. It is a research hot-spot in the field of channel coding in recent years and has a wide range of application prospects in optical communication systems. In this paper, the decoding aspects and performance of LDPC codes are analyzed and compared according to the bit error rate (BER) of LDPC codes. The computer simulation was carried out under additive white Gaussian noise (AWGN) channel and binary phase shift keying (BPSK) modulation. Through theoretical analysis and simulation results, this paper explores the way of multi-rate LDPC decoding. </div>展开更多
With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and...With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and hence causes an increase in the raw bit error rate of data stored in the cells.Recently, low-density parity-check(LDPC)codes have appeared to be a promising solution to combat the interference of MLC NAND flash memory. However, the decoding complexity of the sum-product algorithm(SPA) is extremely high. In this paper, to improve the accuracy of the log likelihood ratio(LLR) information of each bit in each NAND flash memory cell, we adopt a non-uniform detection(N-UD) which uses the average maximum mutual information to determine the value of the soft-decision reference voltages.Furthermore, with an aim to reduce the decoding complexity and improve the decoding performance, we propose a modified soft reliabilitybased iterative majority-logic decoding(MSRBI-MLGD) algorithm, which uses a non-uniform quantizer based on power function to decode LDPC codes. Simulation results show that our design can offer a desirable trade-off between the performance and complexity for high-column-weight LDPC-coded MLC NAND flash memory.展开更多
In this paper, we present a Joint Source-Channel Decoding algorithm (JSCD) for Low-Density Parity Check (LDPC) codes by modifying the Sum-Product Algorithm (SPA) to account for the source redun-dancy, which results fr...In this paper, we present a Joint Source-Channel Decoding algorithm (JSCD) for Low-Density Parity Check (LDPC) codes by modifying the Sum-Product Algorithm (SPA) to account for the source redun-dancy, which results from the neighbouring Huffman coded bits. Simulations demonstrate that in the presence of source redundancy, the proposed algorithm gives better performance than the Separate Source and Channel Decoding algorithm (SSCD).展开更多
A network-coding-based multisource LDPC-coded cooperative MIMO scheme is proposed,where multiple sources transmit their messages to the destination with the assistance from a single relay.The relay cooperates with mul...A network-coding-based multisource LDPC-coded cooperative MIMO scheme is proposed,where multiple sources transmit their messages to the destination with the assistance from a single relay.The relay cooperates with multiple sources simultaneously via network-coding.It avoids the issues of imperfect frequency/timing synchronization and large transmission delay which may be introduced by frequency-division multiple access(FDMA)/code-division multiple access(CDMA)and time-division multiple access(TDMA)manners.The proposed joint″Min-Sum″iterative decoding is effectively carried out in the destination.Such a decoding algorithm agrees with the introduced equivalent joint Tanner graph which can be used to fully characterize LDPC codes employed by the sources and relay.Theoretical analysis and numerical simulation show that the proposed scheme with joint iterative decoding can achieve significant cooperation diversity gain.Furthermore,for the relay,compared with the cascade scheme,the proposed scheme has much lower complexity of LDPC-encoding and is easier to be implemented in the hardware with similar bit error rate(BER)performance.展开更多
基金the National Natural Science Foundation of China (91438116)
文摘In this paper, we present a graphics processing unit(GPU)-based implementation of a weighted bit-reliability based(w BRB) decoder for non-binary LDPC(NB-LDPC) codes. To achieve coalesced memory accesses, an efficient data structure for the w BRB algorithm is proposed. Based on the Single-Instruction Multiple-Threads(SIMT) programming model, a novel mapping strategy with high intra-frame parallelism is presented to improve the latency and throughput performance. Moreover, by using Single-Instruction Multiple-Data(SIMD) intrinsics, four 8-bit message elements are packed into a 32-bit unit and simultaneously processed. Experimental results show that the proposed w BRB decoder provides good tradeoff between error performance and throughput for the codes with relatively large column degrees or high rates.
基金The National Natural Science Foundation of China(No.60871079)
文摘A modified Benes network is proposed to be used as an optimal shuffle network in worldwide interoperability for microwave access （WiMAX） low density parity check （LDPC） decoders, When the size of the input is not a power of two, the modified Benes network can achieve the most optimal performance. This modified Benes network is non-blocking and can perform any sorts of permutations, so it can support 19 modes specified in the WiMAX system. Furthermore, an efficient algorithm to generate the control signals for all the 2 × 2 switches in this network is derived, which can reduce the hardware complexity and overall latency of the modified Benes network. Synthesis results show that the proposed control signal generator can save 25.4% chip area and the overall network latency can be reduced by 36. 2%.
文摘In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC)decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC)LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU)and the variable node unit(VNU)based on min-sum(MS)algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT)is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction.
基金supported in part by National Nature Science Foundation of China under Grant No.61471286,No.61271004the Fundamental Research Funds for the Central Universitiesthe open research fund of Key Laboratory of Information Coding and Transmission,Southwest Jiaotong University(No.2010-03)
文摘Decoding by alternating direction method of multipliers(ADMM) is a promising linear programming decoder for low-density parity-check(LDPC) codes. In this paper, we propose a two-step scheme to lower the error floor of LDPC codes with ADMM penalized decoder.For the undetected errors that cannot be avoided at the decoder side, we modify the code structure slightly to eliminate low-weight code words. For the detected errors induced by small error-prone structures, we propose a post-processing method for the ADMM penalized decoder. Simulation results show that the error floor can be reduced significantly over three illustrated LDPC codes by the proposed two-step scheme.
基金supported by the National Key R&D Program of China(Grant No.2022YFA1005000)the National Natural Science Foundation of China(Grant No.62101308 and 62025110).
文摘Space laser communication(SLC)is an emerging technology to support high-throughput data transmissions in space networks.In this paper,to guarantee the reliability of high-speed SLC links,we aim at practical implementation of low-density paritycheck(LDPC)decoding under resource-restricted space platforms.Particularly,due to the supply restriction and cost issues of high-speed on-board devices such as analog-to-digital converters(ADCs),the input of LDPC decoding will be usually constrained by hard-decision channel output.To tackle this challenge,density-evolution-based theoretical analysis is firstly performed to identify the cause of performance degradation in the conventional binaryinitialized iterative decoding(BIID)algorithm.Then,a computation-efficient decoding algorithm named multiary-initialized iterative decoding with early termination(MIID-ET)is proposed,which improves the error-correcting performance and computation efficiency by using a reliability-based initialization method and a threshold-based decoding termination rule.Finally,numerical simulations are conducted on example codes of rates 7/8 and 1/2 to evaluate the performance of different LDPC decoding algorithms,where the proposed MIID-ET outperforms the BIID with a coding gain of 0.38 dB and variable node calculation saving of 37%.With this advantage,the proposed MIID-ET can notably reduce LDPC decoder’s hardware implementation complexity under the same bit error rate performance,which successfully doubles the total throughput to 10 Gbps on a single-chip FPGA.
文摘Considering that the hardware implementation of the normalized minimum sum(NMS)decoding algorithm for low-density parity-check(LDPC)code is difficult due to the uncertainty of scale factor,an NMS decoding algorithm with variable scale factor is proposed for the near-earth space LDPC codes(8177,7154)in the consultative committee for space data systems(CCSDS)standard.The shift characteristics of field programmable gate array(FPGA)is used to optimize the quantization data of check nodes,and finally the function of LDPC decoder is realized.The simulation and experimental results show that the designed FPGA-based LDPC decoder adopts the scaling factor in the NMS decoding algorithm to improve the decoding performance,simplify the hardware structure,accelerate the convergence speed and improve the error correction ability.
文摘The conventional methodology for designing QC-LDPC decoders is applied for fixed configurations used in wireless communication standards, and the supported largest expansion factor Z (the parallelism of the layered decoding) is a fixed number. In this paper, we study the circular-shifting network for decoding LDPC codes with arbitrary Z factor, especially for decoding large Z (Z P) codes, where P is the decoder parallelism. By buffering the P-length slices from the memory, and assembling the shifted slices in a fixed routine, the P-parallelism shift network can process Z-parallelism circular-shifting tasks. The implementation results show that the proposed network for arbitrary sized data shifting consumes only one times of additional resource cost compared to the traditional solution for only maximum P sized data shifting, and achieves significant saving on area and routing complexity.
文摘A novel low-complexity weighted symbol-flipping algorithm with flipping patterns to decode nonbinary low-density parity-check codes is proposed. The proposed decoding procedure updates the hard-decision received symbol vector iteratively in search of a valid codeword in the symbol vector space. Only one symbol is flipped in each iteration, and symbol flipping function, which is employed as the symbol flipping metric, combines the number of failed checks and the reliabilities of the received bits and calculated symbols. A scheme to avoid infinite loops and select one symbol to flip in high order Galois field search is also proposed. The design of flipping pattern＇s order and depth, which is dependent of the computational requirement and error performance, is also proposed and exemplified. Simulation results show that the algorithm achieves an appealing tradeoff between performance and computational requirement over relatively low Galois field for short to medium code length.
基金the National Natural Science Foundation of China，the National Key Basic Research Program of China，The authors would like to thank all project partners for their valuable contributions and feedbacks
文摘Abstract： The layered decoding algorithm has been widely used in the implementation of Low Density Parity Check （LDPC） decoders, due to its high convergence speed. However, the pipeline operation of the layered decoder may introduce memory access conflicts, which heavily deteriorates the decoder throughput. To essentially deal with the issue of memory access conflicts,
基金Science and Technology on Avionics Integration Laboratory and Aeronautical Science Foundation of China (20115551022)
文摘This paper presents a simple yet effective decoding for general quasi-cyclic low-density parity-check （QC-LDPC） codes, which not only achieves high hardware utility efficiency （HUE）, but also brings about great memory block reduction without any performance degradation. The main idea is to split the check matrix into several row blocks, then to perform the improved mes- sage passing computations sequentially block by block. As the decoding algorithm improves, the sequential tie between the two-phase computations is broken, so that the two-phase computations can be overlapped which bring in high HUE. Two over- lapping schemes are also presented, each of which suits a different situation. In addition, an efficient memory arrangement scheme is proposed to reduce the great memory block requirement of the LDPC decoder. As an example, for the 0.4 rate LDPC code selected from Chinese Digital TV Terrestrial Broadcasting （DTTB）, our decoding saves over 80% memory blocks com- pared with the conventional decoding, and the decoder achieves 0.97 HUE. Finally, the 0.4 rate LDPC decoder is implemented on an FPGA device EP2S30 （speed grade -5）. Using 8 row processing units, the decoder can achieve a maximum net throughput of 28.5 Mbps at 20 iterations.
基金supported in part by the National Natural Science Foundation of China under Grant 61401407in part by the Fundamental Research Funds for the Central Universities under Grant CUC2019B067.
文摘Binary Polar Codes (BPCs) have advantages of high-efficiency and capacity-achieving but suffer from large latency due to the Successive-Cancellation List (SCL) decoding. Non-Binary Polar Codes (NBPCs) have been investigated to obtain the performance gains and reduce latency under the implementation of parallel architectures for multi-bit decoding. However, most of the existing works only focus on the Reed-Solomon matrix-based NBPCs and the probability domain-based non-binary polar decoding, which lack flexible structure and have a large computation amount in the decoding process, while little attention has been paid to general non-binary kernel-based NBPCs and Log-Likelihood Ratio (LLR) based decoding methods. In this paper, we consider a scheme of NBPCs with a general structure over GF(2m). Specifically, we pursue a detailed Monte-Carlo simulation implementation to determine the construction for proposed NBPCs. For non-binary polar decoding, an SCL decoding based on LLRs is proposed for NBPCs, which can be implemented with non-binary kernels of arbitrary size. Moreover, we propose a Perfect Polarization-Based SCL (PPB-SCL) algorithm based on LLRs to reduce decoding complexity by deriving a new update function of path metric for NBPCs and eliminating the path splitting process at perfect polarized (i.e., highly reliable) positions. Simulation results show that the bit error rate of the proposed NBPCs significantly outperforms that of BPCs. In addition, the proposed PPB-SCL decoding obtains about a 40% complexity reduction of SCL decoding for NBPCs.
基金the Aerospace Technology Support Foun-dation of China(No.J04-2005040).
文摘Non-uniform quantization for messages in Low-Density Parity-Check(LDPC)decoding canreduce implementation complexity and mitigate performance loss.But the distribution of messagesvaries in the iterative decoding.This letter proposes a variable non-uniform quantized Belief Propaga-tion(BP)algorithm.The BP decoding is analyzed by density evolution with Gaussian approximation.Since the probability density of messages can be well approximated by Gaussian distribution,by theunbiased estimation of variance,the distribution of messages can be tracked during the iteration.Thusthe non-uniform quantization scheme can be optimized to minimize the distortion.Simulation resultsshow that the variable non-uniform quantization scheme can achieve better error rate performance andfaster decoding convergence than the conventional non-uniform quantization and uniform quantizationschemes.
基金supported by NSF of China (No.61362010,61661005)NSF of Guangxi (No.2015GXNSFAA139290,2014GXNSFBA118276,2012GXNSFAA053217)
文摘An iterative detection/decoding algorithm of correlated sources for the LDPC-based relay systems is presented. The signal from the source-destination(S-D) link is formulated as a highly correlated counterpart from the relay-destination(R-D) link. A special XOR vector is defined using the correlated hard decision information blocks from two decoders and the extrinsic information exchanged between the two decoders is derived by the log-likelihood ratio(LLR) associated with the XOR vector. Such the decoding scheme is different from the traditional turbo-like detection/decoding algorithm, where the extrinsic information is computed by the side information and the soft decoder outputs. Simulations show that the presented algorithm has a slightly better performance than the traditional turbo-like algorithm(Taking the(255,175) EG-LDPC code as an example, it achieves about 0.1 dB performance gains aroundBLER=10^(-4)). Furthermore, the presented algorithm requires fewer computing operations per iteration and has faster convergence rate. For example, the average iteration of the presented algorithm is 33 at SNR=1.8 dB, which is about twice faster than that of the turbo-like algorithm, when decoding the(961,721) QC-LDPC code. Therefore, the presented decoding algorithm of correlated sources provides an alternative decoding solution for the LDPC-based relay systems.
文摘<div style="text-align:justify;"> Low-density parity-check code (LDPC) not only has good performance approaching the Shannon limit, but also has low decoding complexity and flexible structure. It is a research hot-spot in the field of channel coding in recent years and has a wide range of application prospects in optical communication systems. In this paper, the decoding aspects and performance of LDPC codes are analyzed and compared according to the bit error rate (BER) of LDPC codes. The computer simulation was carried out under additive white Gaussian noise (AWGN) channel and binary phase shift keying (BPSK) modulation. Through theoretical analysis and simulation results, this paper explores the way of multi-rate LDPC decoding. </div>
基金supported in part by the NSF of China (61471131, 61771149, 61501126)NSF of Guangdong Province 2016A030310337+1 种基金the open research fund of National Mobile Communications Research Laboratory, Southeast University (No. 2018D02)the Guangdong Province Universities and Colleges Pearl River Scholar Funded Scheme (2017-ZJ022)
文摘With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and hence causes an increase in the raw bit error rate of data stored in the cells.Recently, low-density parity-check(LDPC)codes have appeared to be a promising solution to combat the interference of MLC NAND flash memory. However, the decoding complexity of the sum-product algorithm(SPA) is extremely high. In this paper, to improve the accuracy of the log likelihood ratio(LLR) information of each bit in each NAND flash memory cell, we adopt a non-uniform detection(N-UD) which uses the average maximum mutual information to determine the value of the soft-decision reference voltages.Furthermore, with an aim to reduce the decoding complexity and improve the decoding performance, we propose a modified soft reliabilitybased iterative majority-logic decoding(MSRBI-MLGD) algorithm, which uses a non-uniform quantizer based on power function to decode LDPC codes. Simulation results show that our design can offer a desirable trade-off between the performance and complexity for high-column-weight LDPC-coded MLC NAND flash memory.
文摘In this paper, we present a Joint Source-Channel Decoding algorithm (JSCD) for Low-Density Parity Check (LDPC) codes by modifying the Sum-Product Algorithm (SPA) to account for the source redun-dancy, which results from the neighbouring Huffman coded bits. Simulations demonstrate that in the presence of source redundancy, the proposed algorithm gives better performance than the Separate Source and Channel Decoding algorithm (SSCD).
基金Supported by the Postdoctoral Science Foundation of China(2014M561694)the Science and Technology on Avionics Integration Laboratory and National Aeronautical Science Foundation of China(20105552)
文摘A network-coding-based multisource LDPC-coded cooperative MIMO scheme is proposed,where multiple sources transmit their messages to the destination with the assistance from a single relay.The relay cooperates with multiple sources simultaneously via network-coding.It avoids the issues of imperfect frequency/timing synchronization and large transmission delay which may be introduced by frequency-division multiple access(FDMA)/code-division multiple access(CDMA)and time-division multiple access(TDMA)manners.The proposed joint″Min-Sum″iterative decoding is effectively carried out in the destination.Such a decoding algorithm agrees with the introduced equivalent joint Tanner graph which can be used to fully characterize LDPC codes employed by the sources and relay.Theoretical analysis and numerical simulation show that the proposed scheme with joint iterative decoding can achieve significant cooperation diversity gain.Furthermore,for the relay,compared with the cascade scheme,the proposed scheme has much lower complexity of LDPC-encoding and is easier to be implemented in the hardware with similar bit error rate(BER)performance.
