A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time geneti...A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time genetic task mapping algorithm is proposed during the design stage to generate multiple task mapping solutions which cover a maximum range of chips. Then, during the run, one optimal task mapping solution is selected. Additionally, logical cores are mapped to physically available cores. Both core asymmetry and topological changes are considered in the proposed approach. Experimental results show that the performance yield of the proposed approach is 96% on average, and the communication cost, power consumption and peak temperature are all optimized without loss of performance yield.展开更多
Along with higher and higher integration of intellectual properties(IPs) on a single chip, traditional bus-based system-on-chips(So C) meets several design difficulties(such as low scalability, high power consumption,...Along with higher and higher integration of intellectual properties(IPs) on a single chip, traditional bus-based system-on-chips(So C) meets several design difficulties(such as low scalability, high power consumption,packet latency and clock tree problem). As a promising solution, network-on-chips(No C) has been proposed and widely studied. In this work, a novel algorithm for No C topology synthesis, which is decomposing and cluster refinement(DCR) algorithm, has been proposed to minimize the total power consumption of application-specific No C. This algorithm is composed of two stages: decomposing with cluster generation, and cluster refinement.For partitioning and cluster generation, an initial low-power solution for No C topology is generated. For cluster refinement, the clustering is optimized by performing floorplan to further reduce power consumption. Meanwhile,a good tradeoff between power consumption and CPU time can be achieved. Experimental results show that the proposed method outperforms the existing work.展开更多
As a nanometer-level interconnection,the Optical Network-on-Chip(ONoC)was proposed since it was typically characterized by low latency,high bandwidth and power efficiency. Compared with a 2-Dimensional(2D)design,the 3...As a nanometer-level interconnection,the Optical Network-on-Chip(ONoC)was proposed since it was typically characterized by low latency,high bandwidth and power efficiency. Compared with a 2-Dimensional(2D)design,the 3D integration has the higher packing density and the shorter wire length. Therefore,the 3D ONoC will have the great potential in the future. In this paper,we first discuss the existing ONoC researches,and then design mesh and torus ONoCs from the perspectives of topology,router,and routing module,with the help of 3D integration. A simulation platform is established by using OPNET to compare the performance of 2D and 3D ONoCs in terms of average delay and packet loss rate. The performance comparison between 3D mesh and 3D torus ONoCs is also conducted. The simulation results demonstrate that 3D integration has the advantage of reducing average delay and packet loss rate,and 3D torus ONoC has the better performance compared with 3D mesh solution. Finally,we summarize some future challenges with possible solutions,including microcosmic routing inside optical routers and highly-efficient traffic grooming.展开更多
This paper introduces Twist-routing, a new routing algorithm for faulty on-chip networks, which improves Maze-routing, a face-routing based algorithm which uses deflections in routing, and archives full fault coverage...This paper introduces Twist-routing, a new routing algorithm for faulty on-chip networks, which improves Maze-routing, a face-routing based algorithm which uses deflections in routing, and archives full fault coverage and fast packet delivery. To build Twist-routing algorithm, we use bounding circles, which borrows the idea from GOAFR+ routing algorithm for ad-hoc wireless networks. Unlike Maze-routing, whose path length is unbounded even when the optimal path length is fixed, in Twist-routing, the path length is bounded by the cube of the optimal path length. Our evaluations show that Twist-routing algorithm delivers packets up to 35% faster than Maze-routing with a uniform traffic and Erdos-Rényi failure model, when the failure rate and the injection rate vary.展开更多
Large transmission power consumptions and excessive interconnection lines are two shortcomings which exist in conventional network-on-chips. To improve performance in these areas, this paper proposes a full asynchrono...Large transmission power consumptions and excessive interconnection lines are two shortcomings which exist in conventional network-on-chips. To improve performance in these areas, this paper proposes a full asynchronous serial transmission converter for network-on-chips. By grouping the parallel data between routers into smaller data blocks, interconnection lines between routers can be greatly reduced, which finally brings about saving of power over- heads in the transmission process. Null convention logic units are used to make the circuit quasi-delay insensitive and highly robust. The proposed serial transmission converter and serial channel are implemented based on SMIC 0.18 μm standard CMOS technology. Results demonstrate that this full asynchronous serial transmission converter can save up to three quarters of the interconnection line resources and also reduce up to two-thirds of the power consumption under 32 bit data widths. The proposed full asynchronous serial transmission converter can apply to the on chip network which is sensitive to area and power.展开更多
To improve two shortcomings of conventional network-on-chips,i.e.low utilization rate in channels between routers and excessive interconnection lines,this paper proposes a full asynchronous self-adaptive bi-directiona...To improve two shortcomings of conventional network-on-chips,i.e.low utilization rate in channels between routers and excessive interconnection lines,this paper proposes a full asynchronous self-adaptive bi-directional transmission channel.It can utilize interconnection lines and register resources with high efficiency,and dynamically detect the data transmission state between routers through a direction regulator,which controls the sequencer to automatically adjust the transmission direction of the bi-directional channel,so as to provide a flexible data transmission environment.Null convention logic units are used to make the circuit quasi-delay insensitive and highly robust. The proposed bi-directional transmission channel is implemented based on SMIC 0.18μm standard CMOS technology. Post-layout simulation results demonstrate that this self-adaptive bi-directional channel has better performance on throughput,transmission flexibility and channel bandwidth utilization compared to a conventional single direction channel.Moreover,the proposed channel can save interconnection lines up to 30%and can provide twice the bandwidth resources of a single direction transmission channel.The proposed channel can apply to an on-chip network which has limited resources of registers and interconnection lines.展开更多
Optical network-on-chip(ONoC) systems have emerged as a promising solution to overcome limitations of traditional electronic interconnects. Efficient ONoC architectures rely on optical routers, enabling high-speed dat...Optical network-on-chip(ONoC) systems have emerged as a promising solution to overcome limitations of traditional electronic interconnects. Efficient ONoC architectures rely on optical routers, enabling high-speed data transfer, efficient routing, and scalability. This paper presents a comprehensive survey analyzing optical router designs, specifically microring resonators(MRRs), Mach-Zehnder interferometers(MZIs), and hybrid architectures. Selected comparison criteria, chosen for their critical importance, significantly impact router functionality and performance. By emphasizing these criteria, valuable insights into the strengths and limitations of different designs are gained, facilitating informed decisions and advancements in optical networking. While other factors contribute to performance and efficiency, the chosen criteria consistently address fundamental elements, enabling meaningful evaluation. This work serves as a valuable resource for beginners, providing a solid foundation in understanding ONoC and optical routers. It also offers an in-depth survey for experts, laying the groundwork for further exploration. Additionally, the importance of considering design constraints and requirements when selecting an optimal router design is highlighted. Continued research and innovation will enable the development of efficient optical router solutions that meet the evolving needs of modern computing systems. This survey underscores the significance of ongoing advancements in the field and their potential impact on future technologies.展开更多
In order to ensure the reliability of network-on-chip （NoC） under faulty circumstance, a dynamic fault tolerant routing algorithm is proposed. This algorithm can implement detour routing when there are both static a...In order to ensure the reliability of network-on-chip （NoC） under faulty circumstance, a dynamic fault tolerant routing algorithm is proposed. This algorithm can implement detour routing when there are both static and dynamic permanent faults in the network. That means the packet is able to move around the fanlts to the destination with a non-minimum path. In addition, the multi-level congestion control mechanism gives the algorithm the ability to distribute the load over the whole network and to avoid hotspots around the faults. Simulation results demonstrate the advantage of the proposed routing algorithm in terms of average packet latency and packet loss rate compared with negative-first routing algo- rithm and DyAD routing algorithm in the presence of permanent faults. For the proposed algorithm, it can get much less average packet latency and lead to less than 20% packet loss rate.展开更多
Modulating both the clock frequency and supply voltage of the network-on-chip （NoC） during runtime can reduce the power consumption and heat flux, but will lead to the increase of the latency of NoC. It is necessary...Modulating both the clock frequency and supply voltage of the network-on-chip （NoC） during runtime can reduce the power consumption and heat flux, but will lead to the increase of the latency of NoC. It is necessary to find a tradeoff between power consumption and communication latency. So we propose an analytical latency model which can show us the relationship of them. The proposed model to analyze latency is based on the M/G/1 queuing model, which is suitable for dynamic frequency scaling. The experiment results show that the accuracy of this model is more than 90%.展开更多
A dual-channel access mechanism to overcome the drawback of traditional single-channel access mechanism for network-on-chip （NoC） is proposed. In traditional single-channel access mechanism, every Internet protocol ...A dual-channel access mechanism to overcome the drawback of traditional single-channel access mechanism for network-on-chip （NoC） is proposed. In traditional single-channel access mechanism, every Internet protocol （IP） has only one chan- nel to access the on-chip network. When the network is relatively idle, the injection rate is too small to make good use of the network resource. When the network is relatively busy, the ejection rate is so small that the packets in the network cannot leave immediately, and thus the probability of congestion is increased. In the dual-channel access mechanism, the injection rate of IP and the ejection rate of the network are increased by using two optional channels in network interface （NI） and local port of routers. Therefore, the communication performance is improved. Experimental results show that compared with traditional single-channel access mechanism, the proposed scheme greatly increases the throughput and cuts down the average latency with reasonable area increase.展开更多
This paper introduces a new datapath architecture for reconfigurable processors. The proposed datapath is based on Network-on-Chip approach and facilitates tight coupling of all functional units. Reconfigurable functi...This paper introduces a new datapath architecture for reconfigurable processors. The proposed datapath is based on Network-on-Chip approach and facilitates tight coupling of all functional units. Reconfigurable functional elements can be dynamically allocated for application specific optimizations, enabling polymorphic computing. Using a modified network simulator, performance of several NoC topologies and parameters are investigated with standard benchmark programs, including fine grain and coarse grain computations. Simulation results highlight the flexibility and scalability of the proposed polymorphic NoC processor for a wide range of application domains.展开更多
With further increase of the number of on-chip device, the bus structure has not met the requirements. In order to make better communication between each part, the chip designers need to explore a new structure to sol...With further increase of the number of on-chip device, the bus structure has not met the requirements. In order to make better communication between each part, the chip designers need to explore a new structure to solve the interconnection of on-chip device. The paper proposes a network-on-chip dynamic and adaptive algorithm which selects NoC platform with 2-dimension mesh as the carrier, incorporates communication energy consumption and delay into unified cost function and uses ant colony optimization to realize NOC map facing energy consumption and delay. The experiment indicates that compared with random map, single objective optimization can separately saves （30% - 47 %） and （ 20% - 39%） in communication energy consumption and execution time compared with random map, and joint objective optimization can further excavate the potential of time dimension in mapping scheme dominated by the energy.展开更多
A 3-D topology architeeture based on Spidergon and its generation method are proposed. Aiming at establishing relationships between the topology architecture and the latency, the 3-D topology latency model based on pr...A 3-D topology architeeture based on Spidergon and its generation method are proposed. Aiming at establishing relationships between the topology architecture and the latency, the 3-D topology latency model based on prototype is proposed, and then the optimization topology structure with minimum latency is determined based on it. Meanwhile, in accordance with the structure, the adaptive routing algorithm is designed. The algorithm sets longitudinal direction priority to adaptively searching the equivalent minimum path between the source nodes and the destination nodes in order to increase network throughput. Simulation shows that in case of approximate saturation network, compared with the same scale 3-D mesh structure, 3-D Spidergon has 17% less latency and 16.7% more network throughput.展开更多
First-Input-First-Output (FIFO) buffers are extensively used in contemporary digital processors and System-on-Chips (SoC). There are synchronous FIFOs and asycnrhonous FIFOs. And different sized FIFOs should be implem...First-Input-First-Output (FIFO) buffers are extensively used in contemporary digital processors and System-on-Chips (SoC). There are synchronous FIFOs and asycnrhonous FIFOs. And different sized FIFOs should be implemented in different ways. FIFOs are used not only for the pipeline design within a processor, for the inter-processor communication networks, for example Network-on-Chips (NoCs), but also for the peripherals and the clock domain crossing at the whole SoC level. In this paper, we review the interface, the circuit implementation, and the various usages of FIFOs in various levels of the digital design. We can find that the usage of FIFOs could greatly facilitate the signal storage, signal decoupling, signal transfer, power domain separation and power domain crossing in digital systems. We hope that more attentions are paid to the usages of synchronous and asynchronous FIFOs and more sophististicated usages are discovered by the digital design communities.展开更多
By benefiting from the development of the semiconductor technology, many-core system-on-chips(SoCs)have been widely used in electronic devices. Network-on-chips(NoCs) can address the massive stress of on-chip communic...By benefiting from the development of the semiconductor technology, many-core system-on-chips(SoCs)have been widely used in electronic devices. Network-on-chips(NoCs) can address the massive stress of on-chip communications due to the advantages of high bandwidth, low latency, and good flexibility. Since deep sub-micron era, the reliability has become a critical constraint for integrated circuits. To provide correct data transmission, faulttolerant NoCs have been researched widely in last decades, and many valuable designs have been proposed. This work introduces and summarizes the state-of-the-art technologies for fault diagnosis and fault recovery in faulttolerant NoCs. Moreover, this work makes prospects for the future’s research.展开更多
Among the components on a many-core chip, network-on-chip （NoC） has already contributed a large portion to overall power consumption. Optimizing NoC performance under a given power budget is further complicated to k...Among the components on a many-core chip, network-on-chip （NoC） has already contributed a large portion to overall power consumption. Optimizing NoC performance under a given power budget is further complicated to keep the network connectivity and minimize the detour distances. In this paper, a NoC power budgeting method from the communication perspective is proposed, which intelligently powers off routers/iinks and sets up alternative paths to restrict the power and thermal envelop. The effect of performance optimizaion of the proposed power budgeting mothod is measured based on latency and in the given power budget, 22% latency can be reduced averagely compared with some competing methods when running real benchmarks.展开更多
As feature sizes shrink,low energy consumption,high reliability and high performance become key objectives of network-on-chip(NoC) design.In this paper,an integrated approach is presented to map IP cores onto NoC arch...As feature sizes shrink,low energy consumption,high reliability and high performance become key objectives of network-on-chip(NoC) design.In this paper,an integrated approach is presented to map IP cores onto NoC architecture and assign voltage levels for each link,such that the communication energy is minimized under constraints of bandwidth and reliability.The design space is explored using tabu search.In order to select optimal voltage level for the links,an energy-efficiency driven heuristic algorithm is proposed to perform energy/reliability trade-off by exploiting communication slack.Experimental results show that the ordinary energy optimization techniques ignoring the influence of voltage on fault rates could lead to drastically decreased communication reliability of NoCs,and the proposed approach can produce reliable and energy-efficient implementations.展开更多
Traffic hijacking is a common attack perpetrated on networked systems, where attackers eavesdrop on user transactions, manipulate packet data, and divert traffic to illegitimate locations. Similar attacks can also be ...Traffic hijacking is a common attack perpetrated on networked systems, where attackers eavesdrop on user transactions, manipulate packet data, and divert traffic to illegitimate locations. Similar attacks can also be unleashed in a NoC (Network on Chip) based system where the NoC comes from a third-party vendor and can be engrafted with hardware Trojans. Unlike the attackers on a traditional network, those Trojans are usually small and have limited capacity. This paper targets such a hardware Trojan;Specifically, the Trojan aims to divert traffic packets to unauthorized locations on the NoC. To detect this kind of traffic hijacking, we propose an authentication scheme in which the source and destination addresses are tagged. We develop a custom design for the packet tagging and authentication such that the implementation costs can be greatly reduced. Our experiments on a set of applications show that on average the detection circuitry incurs about 3.37% overhead in area, 2.61% in power, and 0.097% in performance when compared to the baseline design.展开更多
As low power consumption is the main design issue involved in a network on chip (NoC), researchers are concentrating more on both algorithms and architectural approaches. The conventional Dynamic Frequency Scalin...As low power consumption is the main design issue involved in a network on chip (NoC), researchers are concentrating more on both algorithms and architectural approaches. The conventional Dynamic Frequency Scaling (DFS) and history based Frequency Scaling (HDFS) algorithms are utilized to process the energy constrained data traffic. However, these conventional algorithms achieve higher energy efficiencies, and they result in performance degradation due to the auxiliary latency between clock domains. In this paper, we present a variable power optimization interface for NoC using a Finite State Machine (FSM) approach to attain better performance improvement. The parameters are estimated using 45 nm TSMCCMOS technology. In comparison with DFS system, the evaluation results show that FSM-DFS link achieves 81.55% dynamic power savings on the links in the on-chip network, and 37.5% leakage power savings of the link. Also, this proposed work is evaluated for various performance parameters and compared with conventional work. The simulation results are superior to conventional work.展开更多
文摘A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time genetic task mapping algorithm is proposed during the design stage to generate multiple task mapping solutions which cover a maximum range of chips. Then, during the run, one optimal task mapping solution is selected. Additionally, logical cores are mapped to physically available cores. Both core asymmetry and topological changes are considered in the proposed approach. Experimental results show that the performance yield of the proposed approach is 96% on average, and the communication cost, power consumption and peak temperature are all optimized without loss of performance yield.
文摘Along with higher and higher integration of intellectual properties(IPs) on a single chip, traditional bus-based system-on-chips(So C) meets several design difficulties(such as low scalability, high power consumption,packet latency and clock tree problem). As a promising solution, network-on-chips(No C) has been proposed and widely studied. In this work, a novel algorithm for No C topology synthesis, which is decomposing and cluster refinement(DCR) algorithm, has been proposed to minimize the total power consumption of application-specific No C. This algorithm is composed of two stages: decomposing with cluster generation, and cluster refinement.For partitioning and cluster generation, an initial low-power solution for No C topology is generated. For cluster refinement, the clustering is optimized by performing floorplan to further reduce power consumption. Meanwhile,a good tradeoff between power consumption and CPU time can be achieved. Experimental results show that the proposed method outperforms the existing work.
基金supported in part by the National Nat-ural Science Foundation of China(Grant Nos.61401082,61471109,61502075,61672123,91438110,U1301253)the Fundamental Research Funds for Central Universities(Grant Nos.N161604004,N161608001,N150401002,DUT15RC(3)009)Liaoning Bai Qian Wan Talents Program,and National High-Level Personnel Special Support Program for Youth Top-Notch Talent
文摘As a nanometer-level interconnection,the Optical Network-on-Chip(ONoC)was proposed since it was typically characterized by low latency,high bandwidth and power efficiency. Compared with a 2-Dimensional(2D)design,the 3D integration has the higher packing density and the shorter wire length. Therefore,the 3D ONoC will have the great potential in the future. In this paper,we first discuss the existing ONoC researches,and then design mesh and torus ONoCs from the perspectives of topology,router,and routing module,with the help of 3D integration. A simulation platform is established by using OPNET to compare the performance of 2D and 3D ONoCs in terms of average delay and packet loss rate. The performance comparison between 3D mesh and 3D torus ONoCs is also conducted. The simulation results demonstrate that 3D integration has the advantage of reducing average delay and packet loss rate,and 3D torus ONoC has the better performance compared with 3D mesh solution. Finally,we summarize some future challenges with possible solutions,including microcosmic routing inside optical routers and highly-efficient traffic grooming.
文摘This paper introduces Twist-routing, a new routing algorithm for faulty on-chip networks, which improves Maze-routing, a face-routing based algorithm which uses deflections in routing, and archives full fault coverage and fast packet delivery. To build Twist-routing algorithm, we use bounding circles, which borrows the idea from GOAFR+ routing algorithm for ad-hoc wireless networks. Unlike Maze-routing, whose path length is unbounded even when the optimal path length is fixed, in Twist-routing, the path length is bounded by the cube of the optimal path length. Our evaluations show that Twist-routing algorithm delivers packets up to 35% faster than Maze-routing with a uniform traffic and Erdos-Rényi failure model, when the failure rate and the injection rate vary.
基金supported by the National Natural Science Foundation of China(Nos.60676009,60725415,60971066,60803038)the National High-Tech Program of China(Nos.2009AA01Z258,2009AA01Z260).
文摘Large transmission power consumptions and excessive interconnection lines are two shortcomings which exist in conventional network-on-chips. To improve performance in these areas, this paper proposes a full asynchronous serial transmission converter for network-on-chips. By grouping the parallel data between routers into smaller data blocks, interconnection lines between routers can be greatly reduced, which finally brings about saving of power over- heads in the transmission process. Null convention logic units are used to make the circuit quasi-delay insensitive and highly robust. The proposed serial transmission converter and serial channel are implemented based on SMIC 0.18 μm standard CMOS technology. Results demonstrate that this full asynchronous serial transmission converter can save up to three quarters of the interconnection line resources and also reduce up to two-thirds of the power consumption under 32 bit data widths. The proposed full asynchronous serial transmission converter can apply to the on chip network which is sensitive to area and power.
基金Project supported by the National Natural Science Foundation of China(Nos.60725415,60971066)the National High-Tech Research and Development Program of China(Nos.2009AA01Z258,2009AA01Z260)the National Science & Technology Important Project of China(No.2009ZX01034-002-001-005).
文摘To improve two shortcomings of conventional network-on-chips,i.e.low utilization rate in channels between routers and excessive interconnection lines,this paper proposes a full asynchronous self-adaptive bi-directional transmission channel.It can utilize interconnection lines and register resources with high efficiency,and dynamically detect the data transmission state between routers through a direction regulator,which controls the sequencer to automatically adjust the transmission direction of the bi-directional channel,so as to provide a flexible data transmission environment.Null convention logic units are used to make the circuit quasi-delay insensitive and highly robust. The proposed bi-directional transmission channel is implemented based on SMIC 0.18μm standard CMOS technology. Post-layout simulation results demonstrate that this self-adaptive bi-directional channel has better performance on throughput,transmission flexibility and channel bandwidth utilization compared to a conventional single direction channel.Moreover,the proposed channel can save interconnection lines up to 30%and can provide twice the bandwidth resources of a single direction transmission channel.The proposed channel can apply to an on-chip network which has limited resources of registers and interconnection lines.
文摘Optical network-on-chip(ONoC) systems have emerged as a promising solution to overcome limitations of traditional electronic interconnects. Efficient ONoC architectures rely on optical routers, enabling high-speed data transfer, efficient routing, and scalability. This paper presents a comprehensive survey analyzing optical router designs, specifically microring resonators(MRRs), Mach-Zehnder interferometers(MZIs), and hybrid architectures. Selected comparison criteria, chosen for their critical importance, significantly impact router functionality and performance. By emphasizing these criteria, valuable insights into the strengths and limitations of different designs are gained, facilitating informed decisions and advancements in optical networking. While other factors contribute to performance and efficiency, the chosen criteria consistently address fundamental elements, enabling meaningful evaluation. This work serves as a valuable resource for beginners, providing a solid foundation in understanding ONoC and optical routers. It also offers an in-depth survey for experts, laying the groundwork for further exploration. Additionally, the importance of considering design constraints and requirements when selecting an optimal router design is highlighted. Continued research and innovation will enable the development of efficient optical router solutions that meet the evolving needs of modern computing systems. This survey underscores the significance of ongoing advancements in the field and their potential impact on future technologies.
基金Supported by the National High Technology Research and Development Program of China (863 Program) (2002AA1Z149)
文摘In order to ensure the reliability of network-on-chip （NoC） under faulty circumstance, a dynamic fault tolerant routing algorithm is proposed. This algorithm can implement detour routing when there are both static and dynamic permanent faults in the network. That means the packet is able to move around the fanlts to the destination with a non-minimum path. In addition, the multi-level congestion control mechanism gives the algorithm the ability to distribute the load over the whole network and to avoid hotspots around the faults. Simulation results demonstrate the advantage of the proposed routing algorithm in terms of average packet latency and packet loss rate compared with negative-first routing algo- rithm and DyAD routing algorithm in the presence of permanent faults. For the proposed algorithm, it can get much less average packet latency and lead to less than 20% packet loss rate.
基金supported by the National Natural Science Foundation of China under Grant No.61376024 and No.61306024Natural Science Foundation of Guangdong Province under Grant No.S2013040014366Basic Research Programme of Shenzhen No.JCYJ20140417113430642 and JCYJ20140901003939020
文摘Modulating both the clock frequency and supply voltage of the network-on-chip （NoC） during runtime can reduce the power consumption and heat flux, but will lead to the increase of the latency of NoC. It is necessary to find a tradeoff between power consumption and communication latency. So we propose an analytical latency model which can show us the relationship of them. The proposed model to analyze latency is based on the M/G/1 queuing model, which is suitable for dynamic frequency scaling. The experiment results show that the accuracy of this model is more than 90%.
基金supported by the High Technology Research and Development Program of Fujian Province(2010HZ0004-1,2009HZ0003-1)
文摘A dual-channel access mechanism to overcome the drawback of traditional single-channel access mechanism for network-on-chip （NoC） is proposed. In traditional single-channel access mechanism, every Internet protocol （IP） has only one chan- nel to access the on-chip network. When the network is relatively idle, the injection rate is too small to make good use of the network resource. When the network is relatively busy, the ejection rate is so small that the packets in the network cannot leave immediately, and thus the probability of congestion is increased. In the dual-channel access mechanism, the injection rate of IP and the ejection rate of the network are increased by using two optional channels in network interface （NI） and local port of routers. Therefore, the communication performance is improved. Experimental results show that compared with traditional single-channel access mechanism, the proposed scheme greatly increases the throughput and cuts down the average latency with reasonable area increase.
文摘This paper introduces a new datapath architecture for reconfigurable processors. The proposed datapath is based on Network-on-Chip approach and facilitates tight coupling of all functional units. Reconfigurable functional elements can be dynamically allocated for application specific optimizations, enabling polymorphic computing. Using a modified network simulator, performance of several NoC topologies and parameters are investigated with standard benchmark programs, including fine grain and coarse grain computations. Simulation results highlight the flexibility and scalability of the proposed polymorphic NoC processor for a wide range of application domains.
文摘With further increase of the number of on-chip device, the bus structure has not met the requirements. In order to make better communication between each part, the chip designers need to explore a new structure to solve the interconnection of on-chip device. The paper proposes a network-on-chip dynamic and adaptive algorithm which selects NoC platform with 2-dimension mesh as the carrier, incorporates communication energy consumption and delay into unified cost function and uses ant colony optimization to realize NOC map facing energy consumption and delay. The experiment indicates that compared with random map, single objective optimization can separately saves （30% - 47 %） and （ 20% - 39%） in communication energy consumption and execution time compared with random map, and joint objective optimization can further excavate the potential of time dimension in mapping scheme dominated by the energy.
基金Supported by the National Nature Science Foundation of China(61076019)the Aviation Science Foundation(20115552031)the Science and Technology Support Program of Jiangsu Province(BE2010003)~~
文摘A 3-D topology architeeture based on Spidergon and its generation method are proposed. Aiming at establishing relationships between the topology architecture and the latency, the 3-D topology latency model based on prototype is proposed, and then the optimization topology structure with minimum latency is determined based on it. Meanwhile, in accordance with the structure, the adaptive routing algorithm is designed. The algorithm sets longitudinal direction priority to adaptively searching the equivalent minimum path between the source nodes and the destination nodes in order to increase network throughput. Simulation shows that in case of approximate saturation network, compared with the same scale 3-D mesh structure, 3-D Spidergon has 17% less latency and 16.7% more network throughput.
文摘First-Input-First-Output (FIFO) buffers are extensively used in contemporary digital processors and System-on-Chips (SoC). There are synchronous FIFOs and asycnrhonous FIFOs. And different sized FIFOs should be implemented in different ways. FIFOs are used not only for the pipeline design within a processor, for the inter-processor communication networks, for example Network-on-Chips (NoCs), but also for the peripherals and the clock domain crossing at the whole SoC level. In this paper, we review the interface, the circuit implementation, and the various usages of FIFOs in various levels of the digital design. We can find that the usage of FIFOs could greatly facilitate the signal storage, signal decoupling, signal transfer, power domain separation and power domain crossing in digital systems. We hope that more attentions are paid to the usages of synchronous and asynchronous FIFOs and more sophististicated usages are discovered by the digital design communities.
基金supported by the National Natural Science Foundation of China under Grants No.61534002,and No.61701095the Fundamental Research Funds for the Central Universities under Grant No.ZYGX2016J042
文摘By benefiting from the development of the semiconductor technology, many-core system-on-chips(SoCs)have been widely used in electronic devices. Network-on-chips(NoCs) can address the massive stress of on-chip communications due to the advantages of high bandwidth, low latency, and good flexibility. Since deep sub-micron era, the reliability has become a critical constraint for integrated circuits. To provide correct data transmission, faulttolerant NoCs have been researched widely in last decades, and many valuable designs have been proposed. This work introduces and summarizes the state-of-the-art technologies for fault diagnosis and fault recovery in faulttolerant NoCs. Moreover, this work makes prospects for the future’s research.
基金supported by the National Natural Science Foundation of China under Grant No.61376024 and No.61306024Natural Science Foundation of Guangdong Province under Grant No.S2013040014366Basic Research Programme of Shenzhen No.JCYJ20140417113430642 and No.JCYJ20140901003939020
文摘Among the components on a many-core chip, network-on-chip （NoC） has already contributed a large portion to overall power consumption. Optimizing NoC performance under a given power budget is further complicated to keep the network connectivity and minimize the detour distances. In this paper, a NoC power budgeting method from the communication perspective is proposed, which intelligently powers off routers/iinks and sets up alternative paths to restrict the power and thermal envelop. The effect of performance optimizaion of the proposed power budgeting mothod is measured based on latency and in the given power budget, 22% latency can be reduced averagely compared with some competing methods when running real benchmarks.
基金Supported by the Natural Science Foundation of China(No.61003032,61100118)Artificial Intelligence Key Laboratory of Sichuan Province of China(No.2010RY010,2011RYJ05)
文摘As feature sizes shrink,low energy consumption,high reliability and high performance become key objectives of network-on-chip(NoC) design.In this paper,an integrated approach is presented to map IP cores onto NoC architecture and assign voltage levels for each link,such that the communication energy is minimized under constraints of bandwidth and reliability.The design space is explored using tabu search.In order to select optimal voltage level for the links,an energy-efficiency driven heuristic algorithm is proposed to perform energy/reliability trade-off by exploiting communication slack.Experimental results show that the ordinary energy optimization techniques ignoring the influence of voltage on fault rates could lead to drastically decreased communication reliability of NoCs,and the proposed approach can produce reliable and energy-efficient implementations.
文摘Traffic hijacking is a common attack perpetrated on networked systems, where attackers eavesdrop on user transactions, manipulate packet data, and divert traffic to illegitimate locations. Similar attacks can also be unleashed in a NoC (Network on Chip) based system where the NoC comes from a third-party vendor and can be engrafted with hardware Trojans. Unlike the attackers on a traditional network, those Trojans are usually small and have limited capacity. This paper targets such a hardware Trojan;Specifically, the Trojan aims to divert traffic packets to unauthorized locations on the NoC. To detect this kind of traffic hijacking, we propose an authentication scheme in which the source and destination addresses are tagged. We develop a custom design for the packet tagging and authentication such that the implementation costs can be greatly reduced. Our experiments on a set of applications show that on average the detection circuitry incurs about 3.37% overhead in area, 2.61% in power, and 0.097% in performance when compared to the baseline design.
文摘As low power consumption is the main design issue involved in a network on chip (NoC), researchers are concentrating more on both algorithms and architectural approaches. The conventional Dynamic Frequency Scaling (DFS) and history based Frequency Scaling (HDFS) algorithms are utilized to process the energy constrained data traffic. However, these conventional algorithms achieve higher energy efficiencies, and they result in performance degradation due to the auxiliary latency between clock domains. In this paper, we present a variable power optimization interface for NoC using a Finite State Machine (FSM) approach to attain better performance improvement. The parameters are estimated using 45 nm TSMCCMOS technology. In comparison with DFS system, the evaluation results show that FSM-DFS link achieves 81.55% dynamic power savings on the links in the on-chip network, and 37.5% leakage power savings of the link. Also, this proposed work is evaluated for various performance parameters and compared with conventional work. The simulation results are superior to conventional work.
