In this article, we establish the Bessel polynomials with varying large negative parameters and discuss their orthogonality based on the generalized Bessel polynomials. By using the Riemann-Hilbert boundary value prob...In this article, we establish the Bessel polynomials with varying large negative parameters and discuss their orthogonality based on the generalized Bessel polynomials. By using the Riemann-Hilbert boundary value problem on the positive real axis, we get the Riemann-Hilbert characterization of the main Bessel polynomials with varying large negative parameters.展开更多
In order to make systems that are based on unreliable components reliable, the design of fault tolerant architectures will be necessary. Inspired by von Neumann＇s negative AND（NAND）multiplexing and William＇s inter...In order to make systems that are based on unreliable components reliable, the design of fault tolerant architectures will be necessary. Inspired by von Neumann＇s negative AND（NAND）multiplexing and William＇s interwoven redundant logic, this paper presents a fault tolerant technique based on redundancy-modified NAND gates for future nanocomputers. Bifurcation theory is used to analyze fault tolerant ability of the system and the simulation results show that the new system has a much higher fault tolerant ability than the conventional multiplexing based on NAND gates.According to the evaluation, the proposed architecture can tolerate a device error rate of up to 10-1, with multiple redundant components. This fault tolerant technique is potentially useful for future nanoelectronics.展开更多
基金supported by NNSF of China(#11171260)RFDP of Higher Education of China(#20100141110054)
文摘In this article, we establish the Bessel polynomials with varying large negative parameters and discuss their orthogonality based on the generalized Bessel polynomials. By using the Riemann-Hilbert boundary value problem on the positive real axis, we get the Riemann-Hilbert characterization of the main Bessel polynomials with varying large negative parameters.
基金supported by the National Natural Science Foundation of China(61571149)
文摘In order to make systems that are based on unreliable components reliable, the design of fault tolerant architectures will be necessary. Inspired by von Neumann＇s negative AND（NAND）multiplexing and William＇s interwoven redundant logic, this paper presents a fault tolerant technique based on redundancy-modified NAND gates for future nanocomputers. Bifurcation theory is used to analyze fault tolerant ability of the system and the simulation results show that the new system has a much higher fault tolerant ability than the conventional multiplexing based on NAND gates.According to the evaluation, the proposed architecture can tolerate a device error rate of up to 10-1, with multiple redundant components. This fault tolerant technique is potentially useful for future nanoelectronics.
