On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising cloc...On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising clock frequency, therefore it is meaningful to lower the interconnecting bus power in design. In this paper, a simple yet accurate interconnect parasitic capacitance model is presented first and then, based on this model, a novel interconnecting bus optimization method is proposed. Wire spacing is a process for spacing wires for minimum dynamic power, while wire ordering is a process that searches for wire orders that maximally enhance it. The method, i.e., combining wire spacing with wire ordering, focuses on bus dynamic power optimization with a consideration of bus performance requirements. The optimization method is verified based on various nanometer technology parameters, showing that with 50% slack of routing space, 25.71% and 32.65% of power can be saved on average by the proposed optimization method for a global bus and an intermediate bus, respectively, under a 65-nm technology node, compared with 21.78% and 27.68% of power saved on average by uniform spacing technology. The proposed method is especially suitable for computer-aided design of nanometer scale on-chip buses.展开更多
The Godson-2G microprocessor is a high performance SOC which integrates a four-issue 64-bit high performance CPU core （called GS464）, a DDR2/3 controller, a HyperTransport controller, a PCI/PCI-X controller, etc. It...The Godson-2G microprocessor is a high performance SOC which integrates a four-issue 64-bit high performance CPU core （called GS464）, a DDR2/3 controller, a HyperTransport controller, a PCI/PCI-X controller, etc. It is physically implemented in 65 nm CMOS process and reaches the frequency of 1GHz with power consumption less than 4 W. The main challenges of Godson-2G physical implementation include nanometer process technology effects, high performance design targets, and tight schedule. This paper describes the key innovative features of physical design methodology which had been used in Godson-2G physical implementation, with particular emphasis on interconnect driven floorplan generation （ICD-FP）, adapted boundary constraints design optimization （ABC-OPT）, automatic register group clock tree generation methodology （ARG-CTS）.展开更多
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415, 60971066, and 61006028)the National High-Tech Program of China (Grant Nos. 2009AA01Z258 and 2009AA01Z260)the National Key Lab Foundation,China (Grant No. ZHD200904)
文摘On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising clock frequency, therefore it is meaningful to lower the interconnecting bus power in design. In this paper, a simple yet accurate interconnect parasitic capacitance model is presented first and then, based on this model, a novel interconnecting bus optimization method is proposed. Wire spacing is a process for spacing wires for minimum dynamic power, while wire ordering is a process that searches for wire orders that maximally enhance it. The method, i.e., combining wire spacing with wire ordering, focuses on bus dynamic power optimization with a consideration of bus performance requirements. The optimization method is verified based on various nanometer technology parameters, showing that with 50% slack of routing space, 25.71% and 32.65% of power can be saved on average by the proposed optimization method for a global bus and an intermediate bus, respectively, under a 65-nm technology node, compared with 21.78% and 27.68% of power saved on average by uniform spacing technology. The proposed method is especially suitable for computer-aided design of nanometer scale on-chip buses.
基金Supported by the National High Technology Research and Development 863 Program of China under Grant No.2007AA01Z114.
文摘The Godson-2G microprocessor is a high performance SOC which integrates a four-issue 64-bit high performance CPU core （called GS464）, a DDR2/3 controller, a HyperTransport controller, a PCI/PCI-X controller, etc. It is physically implemented in 65 nm CMOS process and reaches the frequency of 1GHz with power consumption less than 4 W. The main challenges of Godson-2G physical implementation include nanometer process technology effects, high performance design targets, and tight schedule. This paper describes the key innovative features of physical design methodology which had been used in Godson-2G physical implementation, with particular emphasis on interconnect driven floorplan generation （ICD-FP）, adapted boundary constraints design optimization （ABC-OPT）, automatic register group clock tree generation methodology （ARG-CTS）.
